diff options
author | Leonid Moiseichuk <lmoiseichuk@nvidia.com> | 2015-05-27 07:19:04 -0400 |
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committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:06 -0500 |
commit | 4b1d9ad4415f1aa044f02afa1f642c3b7855a447 (patch) | |
tree | 28c69ca5245137af7d32fc468c88f0ba571a7dac /drivers/gpu | |
parent | 0c5c1bf61ae1bd3e16a398a7b54e78314c361eb1 (diff) |
gpu: nvgpu: gp10b: add hwpm registers
The produced wrappers for HW PM registers access which are required for
cyclestats support for snapshot buffers mapping.
See commit 589e7a9ffe2a5a70f8803a88fcf8429f553e2fba for tools:nvhost
generators update.
Bug 1573150
Bug 1517458
Change-Id: I9c9332a55f2282c0c626bc8ddbcfdce1289f778b
Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com>
Reviewed-on: http://git-master/r/747717
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h | 205 |
1 files changed, 205 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h new file mode 100644 index 00000000..ea1a61d2 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h | |||
@@ -0,0 +1,205 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_perf_gp10b_h_ | ||
51 | #define _hw_perf_gp10b_h_ | ||
52 | |||
53 | static inline u32 perf_pmasys_control_r(void) | ||
54 | { | ||
55 | return 0x001b4000; | ||
56 | } | ||
57 | static inline u32 perf_pmasys_control_membuf_status_v(u32 r) | ||
58 | { | ||
59 | return (r >> 4) & 0x1; | ||
60 | } | ||
61 | static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) | ||
62 | { | ||
63 | return 0x00000001; | ||
64 | } | ||
65 | static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) | ||
66 | { | ||
67 | return 0x10; | ||
68 | } | ||
69 | static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) | ||
70 | { | ||
71 | return (v & 0x1) << 5; | ||
72 | } | ||
73 | static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) | ||
74 | { | ||
75 | return (r >> 5) & 0x1; | ||
76 | } | ||
77 | static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) | ||
78 | { | ||
79 | return 0x00000001; | ||
80 | } | ||
81 | static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) | ||
82 | { | ||
83 | return 0x20; | ||
84 | } | ||
85 | static inline u32 perf_pmasys_mem_block_r(void) | ||
86 | { | ||
87 | return 0x001b4070; | ||
88 | } | ||
89 | static inline u32 perf_pmasys_mem_block_base_f(u32 v) | ||
90 | { | ||
91 | return (v & 0xfffffff) << 0; | ||
92 | } | ||
93 | static inline u32 perf_pmasys_mem_block_target_f(u32 v) | ||
94 | { | ||
95 | return (v & 0x3) << 28; | ||
96 | } | ||
97 | static inline u32 perf_pmasys_mem_block_target_v(u32 r) | ||
98 | { | ||
99 | return (r >> 28) & 0x3; | ||
100 | } | ||
101 | static inline u32 perf_pmasys_mem_block_target_lfb_v(void) | ||
102 | { | ||
103 | return 0x00000000; | ||
104 | } | ||
105 | static inline u32 perf_pmasys_mem_block_target_lfb_f(void) | ||
106 | { | ||
107 | return 0x0; | ||
108 | } | ||
109 | static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) | ||
110 | { | ||
111 | return 0x00000002; | ||
112 | } | ||
113 | static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) | ||
114 | { | ||
115 | return 0x20000000; | ||
116 | } | ||
117 | static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) | ||
118 | { | ||
119 | return 0x00000003; | ||
120 | } | ||
121 | static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) | ||
122 | { | ||
123 | return 0x30000000; | ||
124 | } | ||
125 | static inline u32 perf_pmasys_mem_block_valid_f(u32 v) | ||
126 | { | ||
127 | return (v & 0x1) << 31; | ||
128 | } | ||
129 | static inline u32 perf_pmasys_mem_block_valid_v(u32 r) | ||
130 | { | ||
131 | return (r >> 31) & 0x1; | ||
132 | } | ||
133 | static inline u32 perf_pmasys_mem_block_valid_true_v(void) | ||
134 | { | ||
135 | return 0x00000001; | ||
136 | } | ||
137 | static inline u32 perf_pmasys_mem_block_valid_true_f(void) | ||
138 | { | ||
139 | return 0x80000000; | ||
140 | } | ||
141 | static inline u32 perf_pmasys_mem_block_valid_false_v(void) | ||
142 | { | ||
143 | return 0x00000000; | ||
144 | } | ||
145 | static inline u32 perf_pmasys_mem_block_valid_false_f(void) | ||
146 | { | ||
147 | return 0x0; | ||
148 | } | ||
149 | static inline u32 perf_pmasys_outbase_r(void) | ||
150 | { | ||
151 | return 0x001b4074; | ||
152 | } | ||
153 | static inline u32 perf_pmasys_outbase_ptr_f(u32 v) | ||
154 | { | ||
155 | return (v & 0x7ffffff) << 5; | ||
156 | } | ||
157 | static inline u32 perf_pmasys_outbaseupper_r(void) | ||
158 | { | ||
159 | return 0x001b4078; | ||
160 | } | ||
161 | static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) | ||
162 | { | ||
163 | return (v & 0xff) << 0; | ||
164 | } | ||
165 | static inline u32 perf_pmasys_outsize_r(void) | ||
166 | { | ||
167 | return 0x001b407c; | ||
168 | } | ||
169 | static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) | ||
170 | { | ||
171 | return (v & 0x7ffffff) << 5; | ||
172 | } | ||
173 | static inline u32 perf_pmasys_mem_bytes_r(void) | ||
174 | { | ||
175 | return 0x001b4084; | ||
176 | } | ||
177 | static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) | ||
178 | { | ||
179 | return (v & 0xfffffff) << 4; | ||
180 | } | ||
181 | static inline u32 perf_pmasys_mem_bump_r(void) | ||
182 | { | ||
183 | return 0x001b4088; | ||
184 | } | ||
185 | static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) | ||
186 | { | ||
187 | return (v & 0xfffffff) << 4; | ||
188 | } | ||
189 | static inline u32 perf_pmasys_enginestatus_r(void) | ||
190 | { | ||
191 | return 0x001b40a4; | ||
192 | } | ||
193 | static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) | ||
194 | { | ||
195 | return (v & 0x1) << 4; | ||
196 | } | ||
197 | static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) | ||
198 | { | ||
199 | return 0x00000001; | ||
200 | } | ||
201 | static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) | ||
202 | { | ||
203 | return 0x10; | ||
204 | } | ||
205 | #endif | ||