diff options
author | Alex Waterman <alexw@nvidia.com> | 2017-08-10 21:31:53 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-14 04:00:26 -0400 |
commit | 4412728b9606a2e2506961ed6e444a344af7ca29 (patch) | |
tree | b3162c3bef064d7ed3b25b3fe27db66f1d2db211 /drivers/gpu | |
parent | df6496384794169c833c82c7aa4d9f1b0100b7e1 (diff) |
gpu: nvgpu: Fix offset units in PRAMIN code
The offset units in the nvgpu_pramin_access_batched() code changes
midway through the function. In the first section it is treated as
bytes but then in the while-loop iterating over the PRAMIN window
and page_alloc_chunks it becomes an offset in words.
This patch leaves the offset field in bytes and converts to words
where needed.
Change-Id: Iba964171679dfc27645238b297ed467a450b5cbc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537079
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/pramin.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/common/pramin.c b/drivers/gpu/nvgpu/common/pramin.c index 688e5ce8..425bfdb4 100644 --- a/drivers/gpu/nvgpu/common/pramin.c +++ b/drivers/gpu/nvgpu/common/pramin.c | |||
@@ -96,10 +96,9 @@ void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem, | |||
96 | break; | 96 | break; |
97 | } | 97 | } |
98 | 98 | ||
99 | offset /= sizeof(u32); | ||
100 | |||
101 | while (size) { | 99 | while (size) { |
102 | byteoff = g->ops.pramin.enter(g, mem, chunk, offset); | 100 | byteoff = g->ops.pramin.enter(g, mem, chunk, |
101 | offset / sizeof(u32)); | ||
103 | start_reg = g->ops.pramin.data032_r(byteoff / sizeof(u32)); | 102 | start_reg = g->ops.pramin.data032_r(byteoff / sizeof(u32)); |
104 | until_end = SZ_1M - (byteoff & (SZ_1M - 1)); | 103 | until_end = SZ_1M - (byteoff & (SZ_1M - 1)); |
105 | 104 | ||
@@ -118,7 +117,7 @@ void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem, | |||
118 | list_entry); | 117 | list_entry); |
119 | offset = 0; | 118 | offset = 0; |
120 | } else { | 119 | } else { |
121 | offset += n / sizeof(u32); | 120 | offset += n; |
122 | } | 121 | } |
123 | } | 122 | } |
124 | } | 123 | } |