gpu: nvgpu: support platform specific physical address translation

On some GPUs certain physical address bits have special meaning. This
patch adds support for setting those bits based on the GMMU attributes
struct.

Jira GPUT19X-10
Bug 200279508

Change-Id: I32b8a028be7fd62af06a60c393a8c9251de0ef3c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master/r/1512600
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

3 files changed, 12 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c
index 55fbcd3f..2abe87c9 100644
--- a/drivers/gpu/nvgpu/common/mm/gmmu.c
+++ b/drivers/gpu/nvgpu/common/mm/gmmu.c
@@ -404,8 +404,9 @@ static int __set_pd_level(struct vm_gk20a *vm,
                  * to be the table of PDEs. When the next level is PTEs the
                  * target addr is the real physical address we are aiming for.
                  */
-                target_addr = next_pd ? nvgpu_pde_phys_addr(g, next_pd) :
-                                        phys_addr;
+                target_addr = next_pd ?
+                        nvgpu_pde_phys_addr(g, next_pd) :
+                        g->ops.mm.gpu_phys_addr(g, attrs, phys_addr);
 
                 l->update_entry(vm, l,
                                 pd, pd_idx,
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index e30a89fe..f365ac94 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -713,6 +713,8 @@ struct gpu_ops {
                         (*get_mmu_levels)(struct gk20a *g, u32 big_page_size);
                 void (*init_pdb)(struct gk20a *g, struct nvgpu_mem *inst_block,
                                 struct vm_gk20a *vm);
+                u64 (*gpu_phys_addr)(struct gk20a *g,
+                                     struct nvgpu_gmmu_attrs *attrs, u64 phys);
                 u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl,
                                          u32 flags);
                 size_t (*get_vidmem_size)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index bdb3b827..d436e985 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -60,6 +60,12 @@ static bool gm20b_mm_is_bar1_supported(struct gk20a *g)
         return true;
 }
 
+u64 gm20b_gpu_phys_addr(struct gk20a *g,
+                        struct nvgpu_gmmu_attrs *attrs, u64 phys)
+{
+        return phys;
+}
+
 void gm20b_init_mm(struct gpu_ops *gops)
 {
         gops->mm.support_sparse = gm20b_mm_support_sparse;
@@ -73,6 +79,7 @@ void gm20b_init_mm(struct gpu_ops *gops)
         gops->mm.set_big_page_size = gm20b_mm_set_big_page_size;
         gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes;
         gops->mm.get_default_big_page_size = gm20b_mm_get_default_big_page_size;
+        gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr;
         gops->mm.get_iova_addr = gk20a_mm_iova_addr;
         gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits;
         gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels;