diff options
author | Alex Frid <afrid@nvidia.com> | 2014-07-26 03:05:01 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:10:38 -0400 |
commit | 40bab00bf706d14914c0ca80a234b9979217453f (patch) | |
tree | 74bc8cc31daea038953eba9ace6cd1e8fbd5d3d5 /drivers/gpu | |
parent | 8c802fc6aec619d2ab9a104b92f1ac7c4f0d963f (diff) |
gpu: nvgpu: Updated GM20b GPCPLL dynamic ramp setup
Setup GPCPLL dynamic ramp coefficients based on update rate (instead
of hard-coding), since on GM20B high reference clock 38.4MHz allows
to use several update rates within supported range.
Bug 1450787
Change-Id: I0e14bcb8e3f65cc164fbb66b4adc688fcee9e2d6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 50 |
1 files changed, 40 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 6211a2cc..aec96341 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -176,10 +176,46 @@ found_match: | |||
176 | return 0; | 176 | return 0; |
177 | } | 177 | } |
178 | 178 | ||
179 | static void clk_setup_slide(struct gk20a *g, u32 clk_u) | ||
180 | { | ||
181 | u32 data, step_a, step_b; | ||
182 | |||
183 | switch (clk_u) { | ||
184 | case 12000: | ||
185 | case 12800: | ||
186 | case 13000: /* only on FPGA */ | ||
187 | step_a = 0x2B; | ||
188 | step_b = 0x0B; | ||
189 | break; | ||
190 | case 19200: | ||
191 | step_a = 0x12; | ||
192 | step_b = 0x08; | ||
193 | break; | ||
194 | case 38400: | ||
195 | step_a = 0x04; | ||
196 | step_b = 0x05; | ||
197 | break; | ||
198 | default: | ||
199 | gk20a_err(dev_from_gk20a(g), "Unexpected reference rate %u kHz", | ||
200 | clk_u); | ||
201 | BUG(); | ||
202 | } | ||
203 | |||
204 | /* setup */ | ||
205 | data = gk20a_readl(g, trim_sys_gpcpll_cfg2_r()); | ||
206 | data = set_field(data, trim_sys_gpcpll_cfg2_pll_stepa_m(), | ||
207 | trim_sys_gpcpll_cfg2_pll_stepa_f(step_a)); | ||
208 | gk20a_writel(g, trim_sys_gpcpll_cfg2_r(), data); | ||
209 | data = gk20a_readl(g, trim_sys_gpcpll_cfg3_r()); | ||
210 | data = set_field(data, trim_sys_gpcpll_cfg3_pll_stepb_m(), | ||
211 | trim_sys_gpcpll_cfg3_pll_stepb_f(step_b)); | ||
212 | gk20a_writel(g, trim_sys_gpcpll_cfg3_r(), data); | ||
213 | } | ||
214 | |||
179 | static int clk_slide_gpc_pll(struct gk20a *g, u32 n) | 215 | static int clk_slide_gpc_pll(struct gk20a *g, u32 n) |
180 | { | 216 | { |
181 | u32 data, coeff; | 217 | u32 data, coeff; |
182 | u32 nold; | 218 | u32 nold, m; |
183 | int ramp_timeout = 500; | 219 | int ramp_timeout = 500; |
184 | 220 | ||
185 | /* get old coefficients */ | 221 | /* get old coefficients */ |
@@ -190,15 +226,9 @@ static int clk_slide_gpc_pll(struct gk20a *g, u32 n) | |||
190 | if (n == nold) | 226 | if (n == nold) |
191 | return 0; | 227 | return 0; |
192 | 228 | ||
193 | /* setup */ | 229 | /* dynamic ramp setup based on update rate */ |
194 | data = gk20a_readl(g, trim_sys_gpcpll_cfg2_r()); | 230 | m = trim_sys_gpcpll_coeff_mdiv_v(coeff); |
195 | data = set_field(data, trim_sys_gpcpll_cfg2_pll_stepa_m(), | 231 | clk_setup_slide(g, g->clk.gpc_pll.clk_in / m); |
196 | trim_sys_gpcpll_cfg2_pll_stepa_f(0x2b)); | ||
197 | gk20a_writel(g, trim_sys_gpcpll_cfg2_r(), data); | ||
198 | data = gk20a_readl(g, trim_sys_gpcpll_cfg3_r()); | ||
199 | data = set_field(data, trim_sys_gpcpll_cfg3_pll_stepb_m(), | ||
200 | trim_sys_gpcpll_cfg3_pll_stepb_f(0xb)); | ||
201 | gk20a_writel(g, trim_sys_gpcpll_cfg3_r(), data); | ||
202 | 232 | ||
203 | /* pll slowdown mode */ | 233 | /* pll slowdown mode */ |
204 | data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r()); | 234 | data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r()); |