diff options
author | Vijayakumar <vsubbu@nvidia.com> | 2017-05-26 02:13:36 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-20 07:24:31 -0400 |
commit | 3afd4af3a73b17317021f3dbca02dbc806a0fc5f (patch) | |
tree | 06adcee8aa26703f45c651e77892c9066c0ae676 /drivers/gpu | |
parent | e50d046ab4354a990d304316630d6aac3c4e9d76 (diff) |
nvgpu: nvgpu: gv11b: Add/Update PMU cmds for ELPG.
This patch:
- Adds a PMU command needed for enabling ELPG.
i.e. command to update sub-feature mask to enable ELPG.
- Adds a new version of PG-GR init param command function
which uses updated command interface.
JIRA GPUT19X-20.
Change-Id: If969c018e2e28264fdc9c897892eb28b021d12f2
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1504873
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 2376e66e..ef4a715d 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | |||
@@ -27,6 +27,9 @@ | |||
27 | 27 | ||
28 | #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> | 28 | #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> |
29 | 29 | ||
30 | #define gv11b_dbg_pmu(fmt, arg...) \ | ||
31 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | ||
32 | |||
30 | #define ALIGN_4KB 12 | 33 | #define ALIGN_4KB 12 |
31 | 34 | ||
32 | static bool gv11b_is_pmu_supported(struct gk20a *g) | 35 | static bool gv11b_is_pmu_supported(struct gk20a *g) |
@@ -147,6 +150,90 @@ static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) | |||
147 | return 0; | 150 | return 0; |
148 | } | 151 | } |
149 | 152 | ||
153 | static void pmu_handle_pg_sub_feature_msg(struct gk20a *g, struct pmu_msg *msg, | ||
154 | void *param, u32 handle, u32 status) | ||
155 | { | ||
156 | gk20a_dbg_fn(""); | ||
157 | |||
158 | if (status != 0) { | ||
159 | nvgpu_err(g, "Sub-feature mask update cmd aborted\n"); | ||
160 | return; | ||
161 | } | ||
162 | |||
163 | gv11b_dbg_pmu("sub-feature mask update is acknowledged from PMU %x\n", | ||
164 | msg->msg.pg.msg_type); | ||
165 | } | ||
166 | |||
167 | static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg, | ||
168 | void *param, u32 handle, u32 status) | ||
169 | { | ||
170 | gk20a_dbg_fn(""); | ||
171 | |||
172 | if (status != 0) { | ||
173 | nvgpu_err(g, "GR PARAM cmd aborted\n"); | ||
174 | return; | ||
175 | } | ||
176 | |||
177 | gv11b_dbg_pmu("GR PARAM is acknowledged from PMU %x\n", | ||
178 | msg->msg.pg.msg_type); | ||
179 | } | ||
180 | |||
181 | static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | ||
182 | { | ||
183 | struct nvgpu_pmu *pmu = &g->pmu; | ||
184 | struct pmu_cmd cmd; | ||
185 | u32 seq; | ||
186 | |||
187 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { | ||
188 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
189 | cmd.hdr.unit_id = PMU_UNIT_PG; | ||
190 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
191 | sizeof(struct pmu_pg_cmd_gr_init_param_v1); | ||
192 | cmd.cmd.pg.gr_init_param_v1.cmd_type = | ||
193 | PMU_PG_CMD_ID_PG_PARAM; | ||
194 | cmd.cmd.pg.gr_init_param_v1.sub_cmd_id = | ||
195 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; | ||
196 | cmd.cmd.pg.gr_init_param_v1.featuremask = | ||
197 | PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; | ||
198 | |||
199 | gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n"); | ||
200 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
201 | pmu_handle_pg_param_msg, pmu, &seq, ~0); | ||
202 | |||
203 | } else | ||
204 | return -EINVAL; | ||
205 | |||
206 | return 0; | ||
207 | } | ||
208 | |||
209 | static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) | ||
210 | { | ||
211 | struct nvgpu_pmu *pmu = &g->pmu; | ||
212 | struct pmu_cmd cmd; | ||
213 | u32 seq; | ||
214 | |||
215 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { | ||
216 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
217 | cmd.hdr.unit_id = PMU_UNIT_PG; | ||
218 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
219 | sizeof(struct pmu_pg_cmd_sub_feature_mask_update); | ||
220 | cmd.cmd.pg.sf_mask_update.cmd_type = | ||
221 | PMU_PG_CMD_ID_PG_PARAM; | ||
222 | cmd.cmd.pg.sf_mask_update.sub_cmd_id = | ||
223 | PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE; | ||
224 | cmd.cmd.pg.sf_mask_update.ctrl_id = | ||
225 | PMU_PG_ELPG_ENGINE_ID_GRAPHICS; | ||
226 | cmd.cmd.pg.sf_mask_update.enabled_mask = | ||
227 | PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; | ||
228 | |||
229 | gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); | ||
230 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
231 | pmu_handle_pg_sub_feature_msg, pmu, &seq, ~0); | ||
232 | } else | ||
233 | return -EINVAL; | ||
234 | |||
235 | return 0; | ||
236 | } | ||
150 | 237 | ||
151 | void gv11b_init_pmu_ops(struct gpu_ops *gops) | 238 | void gv11b_init_pmu_ops(struct gpu_ops *gops) |
152 | { | 239 | { |
@@ -165,4 +252,6 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) | |||
165 | gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; | 252 | gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; |
166 | gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; | 253 | gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; |
167 | gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; | 254 | gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; |
255 | gops->pmu.pmu_pg_init_param = gv11b_pg_gr_init; | ||
256 | gops->pmu.pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask; | ||
168 | } | 257 | } |