diff options
author | sujeet baranwal <sbaranwal@nvidia.com> | 2014-12-22 15:35:15 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 18:06:18 -0400 |
commit | 364156cdcd706510bc37b93a3c7109b45b02d318 (patch) | |
tree | b948ec072fd5752fe5df77b810fa4a6199804b4a /drivers/gpu | |
parent | d1d1fbfb60141f25cad3206f0da974b78c651e71 (diff) |
gpu: nvgpu: Pre-Population of zbc entries
The default zbc entries were never populated in zbc HW table
because the conditional flag "gr->sw_ready" was always set thus
avoided the zbc default loading function call. Now zbc default
loading would happen only during boot time in sw structure.Hw
zbc regs would be loaded from that structure every time a
railgate exit happens.
Bug 1580210
Change-Id: Ie3e40738cbc84cf724c3f3871f15b17a5c84025a
Signed-off-by: Sujeet Baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/662306
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Tested-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 42 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 4 |
4 files changed, 40 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 4d101845..4b48b838 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3805,7 +3805,6 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr) | |||
3805 | { | 3805 | { |
3806 | int i, ret; | 3806 | int i, ret; |
3807 | 3807 | ||
3808 | mutex_init(&gr->zbc_lock); | ||
3809 | for (i = 0; i < gr->max_used_color_index; i++) { | 3808 | for (i = 0; i < gr->max_used_color_index; i++) { |
3810 | struct zbc_color_table *c_tbl = &gr->zbc_col_tbl[i]; | 3809 | struct zbc_color_table *c_tbl = &gr->zbc_col_tbl[i]; |
3811 | struct zbc_entry zbc_val; | 3810 | struct zbc_entry zbc_val; |
@@ -3842,39 +3841,39 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
3842 | struct zbc_entry zbc_val; | 3841 | struct zbc_entry zbc_val; |
3843 | u32 i, err; | 3842 | u32 i, err; |
3844 | 3843 | ||
3844 | mutex_init(&gr->zbc_lock); | ||
3845 | |||
3845 | /* load default color table */ | 3846 | /* load default color table */ |
3846 | zbc_val.type = GK20A_ZBC_TYPE_COLOR; | 3847 | zbc_val.type = GK20A_ZBC_TYPE_COLOR; |
3847 | 3848 | ||
3848 | zbc_val.format = gr_ds_zbc_color_fmt_val_zero_v(); | 3849 | /* Opaque black (i.e. solid black, fmt 0x28 = A8B8G8R8) */ |
3850 | zbc_val.format = gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(); | ||
3849 | for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { | 3851 | for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { |
3850 | zbc_val.color_ds[i] = 0; | 3852 | zbc_val.color_ds[i] = 0; |
3851 | zbc_val.color_l2[i] = 0; | 3853 | zbc_val.color_l2[i] = 0; |
3852 | } | 3854 | } |
3855 | zbc_val.color_l2[0] = 0xff000000; | ||
3856 | zbc_val.color_ds[3] = 0x3f800000; | ||
3853 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); | 3857 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); |
3854 | 3858 | ||
3855 | zbc_val.format = gr_ds_zbc_color_fmt_val_unorm_one_v(); | 3859 | /* Transparent black = (fmt 1 = zero) */ |
3856 | for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { | 3860 | zbc_val.format = gr_ds_zbc_color_fmt_val_zero_v(); |
3857 | zbc_val.color_ds[i] = 0xffffffff; | ||
3858 | zbc_val.color_l2[i] = 0x3f800000; | ||
3859 | } | ||
3860 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); | ||
3861 | |||
3862 | zbc_val.format = gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(); | ||
3863 | for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { | 3861 | for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { |
3864 | zbc_val.color_ds[i] = 0; | 3862 | zbc_val.color_ds[i] = 0; |
3865 | zbc_val.color_l2[i] = 0; | 3863 | zbc_val.color_l2[i] = 0; |
3866 | } | 3864 | } |
3867 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); | 3865 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); |
3868 | 3866 | ||
3869 | zbc_val.format = gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(); | 3867 | /* Opaque white (i.e. solid white) = (fmt 2 = uniform 1) */ |
3868 | zbc_val.format = gr_ds_zbc_color_fmt_val_unorm_one_v(); | ||
3870 | for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { | 3869 | for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { |
3871 | zbc_val.color_ds[i] = 0x3f800000; | 3870 | zbc_val.color_ds[i] = 0x3f800000; |
3872 | zbc_val.color_l2[i] = 0x3f800000; | 3871 | zbc_val.color_l2[i] = 0xffffffff; |
3873 | } | 3872 | } |
3874 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); | 3873 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); |
3875 | 3874 | ||
3876 | if (!err) | 3875 | if (!err) |
3877 | gr->max_default_color_index = 4; | 3876 | gr->max_default_color_index = 3; |
3878 | else { | 3877 | else { |
3879 | gk20a_err(dev_from_gk20a(g), | 3878 | gk20a_err(dev_from_gk20a(g), |
3880 | "fail to load default zbc color table\n"); | 3879 | "fail to load default zbc color table\n"); |
@@ -3885,13 +3884,13 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
3885 | zbc_val.type = GK20A_ZBC_TYPE_DEPTH; | 3884 | zbc_val.type = GK20A_ZBC_TYPE_DEPTH; |
3886 | 3885 | ||
3887 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); | 3886 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); |
3888 | zbc_val.depth = 0; | ||
3889 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); | ||
3890 | |||
3891 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); | ||
3892 | zbc_val.depth = 0x3f800000; | 3887 | zbc_val.depth = 0x3f800000; |
3893 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); | 3888 | err |= gr_gk20a_add_zbc(g, gr, &zbc_val); |
3894 | 3889 | ||
3890 | zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v(); | ||
3891 | zbc_val.depth = 0; | ||
3892 | err = gr_gk20a_add_zbc(g, gr, &zbc_val); | ||
3893 | |||
3895 | if (!err) | 3894 | if (!err) |
3896 | gr->max_default_depth_index = 2; | 3895 | gr->max_default_depth_index = 2; |
3897 | else { | 3896 | else { |
@@ -4311,10 +4310,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4311 | data = gk20a_readl(g, gr_status_mask_r()); | 4310 | data = gk20a_readl(g, gr_status_mask_r()); |
4312 | gk20a_writel(g, gr_status_mask_r(), data & gr->status_disable_mask); | 4311 | gk20a_writel(g, gr_status_mask_r(), data & gr->status_disable_mask); |
4313 | 4312 | ||
4314 | if (gr->sw_ready) | 4313 | gr_gk20a_load_zbc_table(g, gr); |
4315 | gr_gk20a_load_zbc_table(g, gr); | ||
4316 | else | ||
4317 | gr_gk20a_load_zbc_default_table(g, gr); | ||
4318 | 4314 | ||
4319 | g->ops.ltc.init_cbc(g, gr); | 4315 | g->ops.ltc.init_cbc(g, gr); |
4320 | 4316 | ||
@@ -4625,6 +4621,8 @@ static int gk20a_init_gr_setup_sw(struct gk20a *g) | |||
4625 | if (err) | 4621 | if (err) |
4626 | goto clean_up; | 4622 | goto clean_up; |
4627 | 4623 | ||
4624 | gr_gk20a_load_zbc_default_table(g, gr); | ||
4625 | |||
4628 | mutex_init(&gr->ctx_mutex); | 4626 | mutex_init(&gr->ctx_mutex); |
4629 | spin_lock_init(&gr->ch_tlb_lock); | 4627 | spin_lock_init(&gr->ch_tlb_lock); |
4630 | 4628 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index f89bb2a4..4e15af5f 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -1350,6 +1350,10 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) | |||
1350 | { | 1350 | { |
1351 | return 0x00000004; | 1351 | return 0x00000004; |
1352 | } | 1352 | } |
1353 | static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) | ||
1354 | { | ||
1355 | return 0x00000028; | ||
1356 | } | ||
1353 | static inline u32 gr_ds_zbc_z_r(void) | 1357 | static inline u32 gr_ds_zbc_z_r(void) |
1354 | { | 1358 | { |
1355 | return 0x00405818; | 1359 | return 0x00405818; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h index 8783a0bc..e8675bea 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h | |||
@@ -238,4 +238,16 @@ static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(v | |||
238 | { | 238 | { |
239 | return 0x0; | 239 | return 0x0; |
240 | } | 240 | } |
241 | static inline u32 ctxsw_prog_main_image_preemption_options_o(void) | ||
242 | { | ||
243 | return 0x00000060; | ||
244 | } | ||
245 | static inline u32 ctxsw_prog_main_image_preemption_options_control_f(u32 v) | ||
246 | { | ||
247 | return (v & 0x3) << 0; | ||
248 | } | ||
249 | static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f(void) | ||
250 | { | ||
251 | return 0x1; | ||
252 | } | ||
241 | #endif | 253 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 8e4308a3..34cf20de 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -1302,6 +1302,10 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) | |||
1302 | { | 1302 | { |
1303 | return 0x00000004; | 1303 | return 0x00000004; |
1304 | } | 1304 | } |
1305 | static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) | ||
1306 | { | ||
1307 | return 0x00000028; | ||
1308 | } | ||
1305 | static inline u32 gr_ds_zbc_z_r(void) | 1309 | static inline u32 gr_ds_zbc_z_r(void) |
1306 | { | 1310 | { |
1307 | return 0x00405818; | 1311 | return 0x00405818; |