gpu: nvgpu: change stall intr handling order

-Handle pbus and priv stall interrupts first.
 In general critical interrupts should be
 handled before any other non critical ones.

-Dump info enabled with gpu_dbg_intr if priv_ring
 interrupt is flagged by fmodel.

JIRA NVGPU-25

Change-Id: Iee767d8c9c933ceb57532c1b5a7fd7812daf1b6d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1311273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

3 files changed, 17 insertions, 13 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index 107c851c..65f1a119 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Master Control
  *
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -88,6 +88,12 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
 
         gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
 
+        /* handle critical interrupts first */
+        if (mc_intr_0 & mc_intr_0_pbus_pending_f())
+                gk20a_pbus_isr(g);
+        if (mc_intr_0 & mc_intr_0_priv_ring_pending_f())
+                gk20a_priv_ring_isr(g);
+
         for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
                 active_engine_id = g->fifo.active_engines_list[engine_id_idx];
 
@@ -112,12 +118,8 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
                 gk20a_fifo_isr(g);
         if (mc_intr_0 & mc_intr_0_pmu_pending_f())
                 gk20a_pmu_isr(g);
-        if (mc_intr_0 & mc_intr_0_priv_ring_pending_f())
-                gk20a_priv_ring_isr(g);
         if (mc_intr_0 & mc_intr_0_ltc_pending_f())
                 g->ops.ltc.isr(g);
-        if (mc_intr_0 & mc_intr_0_pbus_pending_f())
-                gk20a_pbus_isr(g);
 
         /* sync handled irq counter before re-enabling interrupts */
         atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index a44df1e8..90bd95ac 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -76,8 +76,6 @@ void gk20a_priv_ring_isr(struct gk20a *g)
         u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
         struct gk20a_platform *platform = dev_get_drvdata(g->dev);
 
-        if (platform->is_fmodel)
-                return;
 
         status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
         status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
@@ -90,7 +88,6 @@ void gk20a_priv_ring_isr(struct gk20a *g)
             pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) {
                 gk20a_reset_priv_ring(g);
         }
-
         if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
                 gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
                         gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
@@ -109,6 +106,9 @@ void gk20a_priv_ring_isr(struct gk20a *g)
                 }
         }
 
+        if (platform->is_fmodel)
+                return;
+
         cmd = gk20a_readl(g, pri_ringmaster_command_r());
         cmd = set_field(cmd, pri_ringmaster_command_cmd_m(),
                 pri_ringmaster_command_cmd_ack_interrupt_f());
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 76848159..3f066c37 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -1,7 +1,7 @@
 /*
  * GP20B master
  *
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -113,6 +113,12 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
 
         gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
 
+        /* handle critical interrupts first */
+        if (mc_intr_0 & mc_intr_pbus_pending_f())
+                gk20a_pbus_isr(g);
+        if (mc_intr_0 & mc_intr_priv_ring_pending_f())
+                gk20a_priv_ring_isr(g);
+
         for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
                 active_engine_id = g->fifo.active_engines_list[engine_id_idx];
 
@@ -137,12 +143,8 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
                 gk20a_fifo_isr(g);
         if (mc_intr_0 & mc_intr_pmu_pending_f())
                 gk20a_pmu_isr(g);
-        if (mc_intr_0 & mc_intr_priv_ring_pending_f())
-                gk20a_priv_ring_isr(g);
         if (mc_intr_0 & mc_intr_ltc_pending_f())
                 g->ops.ltc.isr(g);
-        if (mc_intr_0 & mc_intr_pbus_pending_f())
-                gk20a_pbus_isr(g);
 
         gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
                         g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);