diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-08-31 14:15:50 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-15 18:10:48 -0400 |
commit | 31a50f07e4458b43f46a9612e4b27893a50d53b3 (patch) | |
tree | f36998b0a22136740086c753baef9d698f6c1e88 /drivers/gpu | |
parent | f720b309f1ea87a301bcb216983396f3d9c55abc (diff) |
gpu: nvgpu: gv11b: Set pbdma, fb and ctxsw timeout for pre-si
fb and ctxsw timeout detection should be disabled for simulation
architectures. Also set timeouts to max for pbdma, fb and
ctxsw timeouts.
Bug 200289427
Change-Id: I8723d5ee9ea2535f401b1972c8c14ffab8f9504a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549522
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 43 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 32 |
2 files changed, 69 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b4e4b875..6f9e44fb 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1166,10 +1166,27 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) | |||
1166 | 1166 | ||
1167 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); | 1167 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); |
1168 | nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout); | 1168 | nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout); |
1169 | if (!nvgpu_platform_is_silicon(g)) { | ||
1170 | timeout = set_field(timeout, fifo_fb_timeout_period_m(), | ||
1171 | fifo_fb_timeout_period_max_f()); | ||
1172 | timeout = set_field(timeout, fifo_fb_timeout_detection_m(), | ||
1173 | fifo_fb_timeout_detection_disabled_f()); | ||
1174 | nvgpu_log_info(g, "new fifo_fb_timeout reg val = 0x%08x", | ||
1175 | timeout); | ||
1176 | gk20a_writel(g, fifo_fb_timeout_r(), timeout); | ||
1177 | } | ||
1178 | |||
1169 | for (i = 0; i < host_num_pbdma; i++) { | 1179 | for (i = 0; i < host_num_pbdma; i++) { |
1170 | timeout = gk20a_readl(g, pbdma_timeout_r(i)); | 1180 | timeout = gk20a_readl(g, pbdma_timeout_r(i)); |
1171 | nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", | 1181 | nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", |
1172 | timeout); | 1182 | timeout); |
1183 | if (!nvgpu_platform_is_silicon(g)) { | ||
1184 | timeout = set_field(timeout, pbdma_timeout_period_m(), | ||
1185 | pbdma_timeout_period_max_f()); | ||
1186 | nvgpu_log_info(g, "new pbdma_timeout reg val = 0x%08x", | ||
1187 | timeout); | ||
1188 | gk20a_writel(g, pbdma_timeout_r(i), timeout); | ||
1189 | } | ||
1173 | } | 1190 | } |
1174 | 1191 | ||
1175 | /* clear and enable pbdma interrupt */ | 1192 | /* clear and enable pbdma interrupt */ |
@@ -1189,12 +1206,26 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) | |||
1189 | /* clear ctxsw timeout interrupts */ | 1206 | /* clear ctxsw timeout interrupts */ |
1190 | gk20a_writel(g, fifo_intr_ctxsw_timeout_r(), ~0); | 1207 | gk20a_writel(g, fifo_intr_ctxsw_timeout_r(), ~0); |
1191 | 1208 | ||
1192 | /* enable ctxsw timeout */ | 1209 | if (nvgpu_platform_is_silicon(g)) { |
1193 | timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; | 1210 | /* enable ctxsw timeout */ |
1194 | timeout = scale_ptimer(timeout, | 1211 | timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; |
1195 | ptimer_scalingfactor10x(g->ptimer_src_freq)); | 1212 | timeout = scale_ptimer(timeout, |
1196 | timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); | 1213 | ptimer_scalingfactor10x(g->ptimer_src_freq)); |
1197 | gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); | 1214 | timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); |
1215 | gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); | ||
1216 | } else { | ||
1217 | timeout = gk20a_readl(g, fifo_eng_ctxsw_timeout_r()); | ||
1218 | nvgpu_log_info(g, "fifo_eng_ctxsw_timeout reg val = 0x%08x", | ||
1219 | timeout); | ||
1220 | timeout = set_field(timeout, fifo_eng_ctxsw_timeout_period_m(), | ||
1221 | fifo_eng_ctxsw_timeout_period_max_f()); | ||
1222 | timeout = set_field(timeout, | ||
1223 | fifo_eng_ctxsw_timeout_detection_m(), | ||
1224 | fifo_eng_ctxsw_timeout_detection_disabled_f()); | ||
1225 | nvgpu_log_info(g, "new fifo_eng_ctxsw_timeout reg val = 0x%08x", | ||
1226 | timeout); | ||
1227 | gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); | ||
1228 | } | ||
1198 | 1229 | ||
1199 | /* clear runlist interrupts */ | 1230 | /* clear runlist interrupts */ |
1200 | gk20a_writel(g, fifo_intr_runlist_r(), ~0); | 1231 | gk20a_writel(g, fifo_intr_runlist_r(), ~0); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index e98c9f76..04d6f0f4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | |||
@@ -382,6 +382,18 @@ static inline u32 fifo_fb_timeout_period_init_f(void) | |||
382 | { | 382 | { |
383 | return 0x3c00; | 383 | return 0x3c00; |
384 | } | 384 | } |
385 | static inline u32 fifo_fb_timeout_detection_m(void) | ||
386 | { | ||
387 | return 0x1 << 31; | ||
388 | } | ||
389 | static inline u32 fifo_fb_timeout_detection_enabled_f(void) | ||
390 | { | ||
391 | return 0x80000000; | ||
392 | } | ||
393 | static inline u32 fifo_fb_timeout_detection_disabled_f(void) | ||
394 | { | ||
395 | return 0x0; | ||
396 | } | ||
385 | static inline u32 fifo_sched_disable_r(void) | 397 | static inline u32 fifo_sched_disable_r(void) |
386 | { | 398 | { |
387 | return 0x00002630; | 399 | return 0x00002630; |
@@ -538,18 +550,38 @@ static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) | |||
538 | { | 550 | { |
539 | return (v & 0x7fffffff) << 0; | 551 | return (v & 0x7fffffff) << 0; |
540 | } | 552 | } |
553 | static inline u32 fifo_eng_ctxsw_timeout_period_m(void) | ||
554 | { | ||
555 | return 0x7fffffff << 0; | ||
556 | } | ||
541 | static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) | 557 | static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) |
542 | { | 558 | { |
543 | return (r >> 0) & 0x7fffffff; | 559 | return (r >> 0) & 0x7fffffff; |
544 | } | 560 | } |
561 | static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void) | ||
562 | { | ||
563 | return 0x3fffff; | ||
564 | } | ||
565 | static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void) | ||
566 | { | ||
567 | return 0x7fffffff; | ||
568 | } | ||
545 | static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) | 569 | static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) |
546 | { | 570 | { |
547 | return (v & 0x1) << 31; | 571 | return (v & 0x1) << 31; |
548 | } | 572 | } |
573 | static inline u32 fifo_eng_ctxsw_timeout_detection_m(void) | ||
574 | { | ||
575 | return 0x1 << 31; | ||
576 | } | ||
549 | static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) | 577 | static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) |
550 | { | 578 | { |
551 | return 0x80000000; | 579 | return 0x80000000; |
552 | } | 580 | } |
581 | static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void) | ||
582 | { | ||
583 | return 0x0; | ||
584 | } | ||
553 | static inline u32 fifo_pbdma_status_r(u32 i) | 585 | static inline u32 fifo_pbdma_status_r(u32 i) |
554 | { | 586 | { |
555 | return 0x00003080 + i*4; | 587 | return 0x00003080 + i*4; |