gpu: nvgpu: gv11b: update ramfc

Updated ramfc:
 - To include channel veid info
 - Set valid context bit
 - Enabled userd writeback

JIRA GV11B-11

Change-Id: I0e8c62fe0dee02071b0ca60f157151038ab5c09b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1237764
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 files changed, 133 insertions, 19 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index c6e0f0a2..0e1c1999 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -24,6 +24,9 @@
 #include "hw_ccsr_gv11b.h"
 #include "hw_usermode_gv11b.h"
 
+#define CHANNEL_INFO_VEID0  0
+#define PBDMA_SUBDEVICE_ID  1
+
 static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
 {
 
@@ -82,6 +85,88 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist)
                         runlist[0], runlist[1], runlist[2], runlist[3]);
 }
 
+static void gv11b_userd_writeback_config(struct gk20a *g)
+{
+        gk20a_writel(g, fifo_userd_writeback_r(), fifo_userd_writeback_timer_f(
+                                fifo_userd_writeback_timer_100us_v()));
+
+
+}
+
+static int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
+                u64 gpfifo_base, u32 gpfifo_entries, u32 flags)
+{
+        struct gk20a *g = c->g;
+        struct mem_desc *mem = &c->inst_block;
+        u32 data;
+
+        gk20a_dbg_fn("");
+
+        gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v());
+
+        gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(),
+                pbdma_gp_base_offset_f(
+                u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
+
+        gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
+                pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
+                pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
+
+        gk20a_mem_wr32(g, mem, ram_fc_signature_w(),
+                c->g->ops.fifo.get_pbdma_signature(c->g));
+
+        gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(),
+                pbdma_pb_header_priv_user_f() |
+                pbdma_pb_header_method_zero_f() |
+                pbdma_pb_header_subchannel_zero_f() |
+                pbdma_pb_header_level_main_f() |
+                pbdma_pb_header_first_true_f() |
+                pbdma_pb_header_type_inc_f());
+
+        gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(),
+                pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) |
+                pbdma_subdevice_status_active_f() |
+                pbdma_subdevice_channel_dma_enable_f());
+
+        gk20a_mem_wr32(g, mem, ram_fc_target_w(),
+                pbdma_target_eng_ctx_valid_true_f() |
+                pbdma_target_engine_sw_f());
+
+        gk20a_mem_wr32(g, mem, ram_fc_acquire_w(),
+                channel_gk20a_pbdma_acquire_val(c));
+
+        gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
+                pbdma_runlist_timeslice_timeout_128_f() |
+                pbdma_runlist_timeslice_timescale_3_f() |
+                pbdma_runlist_timeslice_enable_true_f());
+
+
+        gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid));
+
+        /* Until full subcontext is supported, always use VEID0 */
+        gk20a_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
+                pbdma_set_channel_info_scg_type_graphics_compute0_f() |
+                pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0));
+
+        if (c->is_privileged_channel) {
+                /* Set privilege level for channel */
+                gk20a_mem_wr32(g, mem, ram_fc_config_w(),
+                        pbdma_config_auth_level_privileged_f());
+
+                gk20a_channel_setup_ramfc_for_privileged_channel(c);
+        }
+
+        /* Enable userd writeback */
+        data = gk20a_mem_rd32(g, mem, ram_fc_config_w());
+        data = data | pbdma_config_userd_writeback_enable_f();
+        gk20a_mem_wr32(g, mem, ram_fc_config_w(),data);
+
+        gv11b_userd_writeback_config(g);
+
+        return channel_gp10b_commit_userd(c);
+}
+
+
 static void gv11b_ring_channel_doorbell(struct channel_gk20a *c)
 {
         gk20a_dbg_info("channel ring door bell %d\n", c->hw_chid);
@@ -131,4 +216,5 @@ void gv11b_init_fifo(struct gpu_ops *gops)
         gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos;
         gops->fifo.userd_gp_get = gv11b_userd_gp_get;
         gops->fifo.userd_gp_put = gv11b_userd_gp_put;
+        gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc;
 }
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
index 7e9e2743..8ea2e06a 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
@@ -70,6 +70,34 @@ static inline u32 fifo_bar1_base_valid_true_f(void)
 {
         return 0x10000000;
 }
+static inline u32 fifo_userd_writeback_r(void)
+{
+        return 0x0000225c;
+}
+static inline u32 fifo_userd_writeback_timer_f(u32 v)
+{
+        return (v & 0xff) << 0;
+}
+static inline u32 fifo_userd_writeback_timer_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 fifo_userd_writeback_timer_shorter_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 fifo_userd_writeback_timer_100us_v(void)
+{
+        return 0x00000064;
+}
+static inline u32 fifo_userd_writeback_timescale_f(u32 v)
+{
+        return (v & 0xf) << 12;
+}
+static inline u32 fifo_userd_writeback_timescale_0_v(void)
+{
+        return 0x00000000;
+}
 static inline u32 fifo_runlist_base_r(void)
 {
         return 0x00002270;
diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
index be8089d8..c4d3a631 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
@@ -342,6 +342,14 @@ static inline u32 pbdma_config_auth_level_privileged_f(void)
 {
         return 0x100;
 }
+static inline u32 pbdma_config_userd_writeback_disable_f(void)
+{
+        return 0x0;
+}
+static inline u32 pbdma_config_userd_writeback_enable_f(void)
+{
+        return 0x1000;
+}
 static inline u32 pbdma_userd_hi_r(u32 i)
 {
         return 0x0004000c + i*8192;
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
index 46772ff4..11874209 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
@@ -178,6 +178,10 @@ static inline u32 ram_in_engine_cs_fg_f(void)
 {
         return 0x8;
 }
+static inline u32 ram_in_engine_wfi_mode_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
 static inline u32 ram_in_engine_wfi_mode_w(void)
 {
         return 132;
@@ -186,17 +190,13 @@ static inline u32 ram_in_engine_wfi_mode_physical_v(void)
 {
         return 0x00000000;
 }
-static inline u32 ram_in_engine_wfi_mode_physical_f(void)
-{
-        return 0x0;
-}
 static inline u32 ram_in_engine_wfi_mode_virtual_v(void)
 {
         return 0x00000001;
 }
-static inline u32 ram_in_engine_wfi_mode_virtual_f(void)
+static inline u32 ram_in_engine_wfi_target_f(u32 v)
 {
-        return 0x4;
+        return (v & 0x3) << 0;
 }
 static inline u32 ram_in_engine_wfi_target_w(void)
 {
@@ -206,26 +206,14 @@ static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void)
 {
         return 0x00000002;
 }
-static inline u32 ram_in_engine_wfi_target_sys_mem_coh_f(void)
-{
-        return 0x2;
-}
-static inline u32 ram_in_engine_wfi_target_sys_mem_nocoh_v(void)
+static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void)
 {
         return 0x00000003;
 }
-static inline u32 ram_in_engine_wfi_target_sys_mem_nocoh_f(void)
-{
-        return 0x3;
-}
 static inline u32 ram_in_engine_wfi_target_local_mem_v(void)
 {
         return 0x00000000;
 }
-static inline u32 ram_in_engine_wfi_target_local_mem_f(void)
-{
-        return 0x0;
-}
 static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v)
 {
         return (v & 0xfffff) << 12;
@@ -582,6 +570,10 @@ static inline u32 ram_fc_chid_id_w(void)
 {
         return 0;
 }
+static inline u32 ram_fc_config_w(void)
+{
+        return 61;
+}
 static inline u32 ram_fc_runlist_timeslice_w(void)
 {
         return 62;