diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-05-11 15:13:05 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-06-06 10:25:51 -0400 |
commit | 2d7c96c5e90b18ba6ef61ff866c2846c71388b42 (patch) | |
tree | e9c36feb010e43274d11efff274060a3276296cb /drivers/gpu | |
parent | 85d0bc498d8329717fe5b0d947b8458e38ff0982 (diff) |
gpu: nvgpu: Disable channel when updating SMPC WAR
When updating SMPC WAR for channel, it needs to be kicked out. This
ensures that the updated information is re-read from context header.
Bug 1579548
Change-Id: Ia65bdb638cec7125021a8e60c365b83085efe0d4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/741322
Reviewed-on: http://git-master/r/743859
(cherry picked from commit dd6cd54b41d63ae94d066b8d98a40c6f6a2196e5)
Reviewed-on: http://git-master/r/753283
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 603fc3a4..b2fea5b8 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1566,6 +1566,15 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g, | |||
1566 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; | 1566 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; |
1567 | void *ctx_ptr = NULL; | 1567 | void *ctx_ptr = NULL; |
1568 | u32 data; | 1568 | u32 data; |
1569 | int ret; | ||
1570 | |||
1571 | c->g->ops.fifo.disable_channel(c); | ||
1572 | ret = c->g->ops.fifo.preempt_channel(c->g, c->hw_chid); | ||
1573 | if (ret) { | ||
1574 | gk20a_err(dev_from_gk20a(g), | ||
1575 | "failed to preempt channel\n"); | ||
1576 | return ret; | ||
1577 | } | ||
1569 | 1578 | ||
1570 | /* Channel gr_ctx buffer is gpu cacheable. | 1579 | /* Channel gr_ctx buffer is gpu cacheable. |
1571 | Flush and invalidate before cpu update. */ | 1580 | Flush and invalidate before cpu update. */ |
@@ -1587,6 +1596,11 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g, | |||
1587 | 1596 | ||
1588 | vunmap(ctx_ptr); | 1597 | vunmap(ctx_ptr); |
1589 | 1598 | ||
1599 | /* enable channel */ | ||
1600 | gk20a_writel(c->g, ccsr_channel_r(c->hw_chid), | ||
1601 | gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) | | ||
1602 | ccsr_channel_enable_set_true_f()); | ||
1603 | |||
1590 | return 0; | 1604 | return 0; |
1591 | } | 1605 | } |
1592 | 1606 | ||