diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-06-30 02:12:17 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-04 02:44:30 -0400 |
commit | 2cf964d175abc0f3eae9ed0e01e6eeed5cd6b4da (patch) | |
tree | dc91c30fdfcf4ee37ff830dcffc7b15c8b5add14 /drivers/gpu | |
parent | fbeca4a8414c03a1564d7a370964187be51a3e6c (diff) |
gpu: nvgpu: Falcon controller halt interrupt status clear
- Added nvgpu_flcn_clear_halt_intr_status() to
Wait for halt interrupt status clear by
clear_halt_interrupt_status() HAL within timeout
- Added gk20a_flcn_clear_halt_interrupt_status()
to clear falcon controller halt interrupt status
- Replaced flacon halt interrupt clear with
nvgpu_flcn_clear_halt_intr_status() method
NVGPU JIRA-99
Change-Id: I762a3c01cd1d02028eb6aaa9898a50be94376619
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1511333
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/bios_gm206.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/falcon.h | 3 |
6 files changed, 68 insertions, 41 deletions
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index ba2fb3fe..3795dd09 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -122,6 +122,34 @@ int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout) | |||
122 | return status; | 122 | return status; |
123 | } | 123 | } |
124 | 124 | ||
125 | int nvgpu_flcn_clear_halt_intr_status(struct nvgpu_falcon *flcn, | ||
126 | unsigned int timeout) | ||
127 | { | ||
128 | struct gk20a *g = flcn->g; | ||
129 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | ||
130 | struct nvgpu_timeout to; | ||
131 | int status = 0; | ||
132 | |||
133 | if (!flcn_ops->clear_halt_interrupt_status) { | ||
134 | nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", | ||
135 | flcn->flcn_id); | ||
136 | return -EINVAL; | ||
137 | } | ||
138 | |||
139 | nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER); | ||
140 | do { | ||
141 | if (flcn_ops->clear_halt_interrupt_status(flcn)) | ||
142 | break; | ||
143 | |||
144 | nvgpu_udelay(1); | ||
145 | } while (!nvgpu_timeout_expired(&to)); | ||
146 | |||
147 | if (nvgpu_timeout_peek_expired(&to)) | ||
148 | status = -EBUSY; | ||
149 | |||
150 | return status; | ||
151 | } | ||
152 | |||
125 | bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn) | 153 | bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn) |
126 | { | 154 | { |
127 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | 155 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; |
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index 328f5bf7..b52652e2 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | |||
@@ -38,6 +38,26 @@ static int gk20a_flcn_reset(struct nvgpu_falcon *flcn) | |||
38 | return status; | 38 | return status; |
39 | } | 39 | } |
40 | 40 | ||
41 | static bool gk20a_flcn_clear_halt_interrupt_status(struct nvgpu_falcon *flcn) | ||
42 | { | ||
43 | struct gk20a *g = flcn->g; | ||
44 | u32 base_addr = flcn->flcn_base; | ||
45 | u32 data = 0; | ||
46 | bool status = false; | ||
47 | |||
48 | gk20a_writel(g, base_addr + falcon_falcon_irqsclr_r(), | ||
49 | gk20a_readl(g, base_addr + falcon_falcon_irqsclr_r()) | | ||
50 | (0x10)); | ||
51 | data = gk20a_readl(g, (base_addr + falcon_falcon_irqstat_r())); | ||
52 | |||
53 | if ((data & falcon_falcon_irqstat_halt_true_f()) != | ||
54 | falcon_falcon_irqstat_halt_true_f()) | ||
55 | /*halt irq is clear*/ | ||
56 | status = true; | ||
57 | |||
58 | return status; | ||
59 | } | ||
60 | |||
41 | static void gk20a_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable) | 61 | static void gk20a_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable) |
42 | { | 62 | { |
43 | struct gk20a *g = flcn->g; | 63 | struct gk20a *g = flcn->g; |
@@ -275,6 +295,8 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn) | |||
275 | 295 | ||
276 | flcn_ops->reset = gk20a_flcn_reset; | 296 | flcn_ops->reset = gk20a_flcn_reset; |
277 | flcn_ops->set_irq = gk20a_flcn_set_irq; | 297 | flcn_ops->set_irq = gk20a_flcn_set_irq; |
298 | flcn_ops->clear_halt_interrupt_status = | ||
299 | gk20a_flcn_clear_halt_interrupt_status; | ||
278 | flcn_ops->is_falcon_cpu_halted = gk20a_is_falcon_cpu_halted; | 300 | flcn_ops->is_falcon_cpu_halted = gk20a_is_falcon_cpu_halted; |
279 | flcn_ops->is_falcon_idle = gk20a_is_falcon_idle; | 301 | flcn_ops->is_falcon_idle = gk20a_is_falcon_idle; |
280 | flcn_ops->is_falcon_scrubbing_done = gk20a_is_falcon_scrubbing_done; | 302 | flcn_ops->is_falcon_scrubbing_done = gk20a_is_falcon_scrubbing_done; |
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c index 7aec21e7..be089f2f 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.c +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c | |||
@@ -154,9 +154,8 @@ static int gm206_bios_devinit(struct gk20a *g) | |||
154 | if (nvgpu_timeout_peek_expired(&timeout)) | 154 | if (nvgpu_timeout_peek_expired(&timeout)) |
155 | err = -ETIMEDOUT; | 155 | err = -ETIMEDOUT; |
156 | 156 | ||
157 | gk20a_writel(g, pwr_falcon_irqsclr_r(), | 157 | nvgpu_flcn_clear_halt_intr_status(g->pmu.flcn, |
158 | pwr_falcon_irqstat_halt_true_f()); | 158 | gk20a_get_gr_idle_timeout(g)); |
159 | gk20a_readl(g, pwr_falcon_irqsclr_r()); | ||
160 | 159 | ||
161 | out: | 160 | out: |
162 | gk20a_dbg_fn("done"); | 161 | gk20a_dbg_fn("done"); |
@@ -200,9 +199,8 @@ static int gm206_bios_preos(struct gk20a *g) | |||
200 | goto out; | 199 | goto out; |
201 | } | 200 | } |
202 | 201 | ||
203 | gk20a_writel(g, pwr_falcon_irqsclr_r(), | 202 | nvgpu_flcn_clear_halt_intr_status(g->pmu.flcn, |
204 | pwr_falcon_irqstat_halt_true_f()); | 203 | gk20a_get_gr_idle_timeout(g)); |
205 | gk20a_readl(g, pwr_falcon_irqsclr_r()); | ||
206 | 204 | ||
207 | out: | 205 | out: |
208 | gk20a_dbg_fn("done"); | 206 | gk20a_dbg_fn("done"); |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index e440e179..ee861933 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1517,23 +1517,11 @@ static int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms) | |||
1517 | */ | 1517 | */ |
1518 | static int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout_ms) | 1518 | static int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout_ms) |
1519 | { | 1519 | { |
1520 | u32 data = 0; | 1520 | struct nvgpu_pmu *pmu = &g->pmu; |
1521 | struct nvgpu_timeout timeout; | 1521 | int status = 0; |
1522 | |||
1523 | nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER); | ||
1524 | |||
1525 | do { | ||
1526 | gk20a_writel(g, pwr_falcon_irqsclr_r(), | ||
1527 | gk20a_readl(g, pwr_falcon_irqsclr_r()) | (0x10)); | ||
1528 | data = gk20a_readl(g, (pwr_falcon_irqstat_r())); | ||
1529 | |||
1530 | if ((data & pwr_falcon_irqstat_halt_true_f()) != | ||
1531 | pwr_falcon_irqstat_halt_true_f()) | ||
1532 | /*halt irq is clear*/ | ||
1533 | return 0; | ||
1534 | 1522 | ||
1535 | nvgpu_udelay(1); | 1523 | if (nvgpu_flcn_clear_halt_intr_status(pmu->flcn, timeout_ms)) |
1536 | } while (!nvgpu_timeout_expired(&timeout)); | 1524 | status = -EBUSY; |
1537 | 1525 | ||
1538 | return -ETIMEDOUT; | 1526 | return status; |
1539 | } | 1527 | } |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 20171309..0f265710 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -34,24 +34,12 @@ | |||
34 | 34 | ||
35 | int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout) | 35 | int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout) |
36 | { | 36 | { |
37 | u32 data = 0; | 37 | int status = 0; |
38 | struct nvgpu_timeout to; | 38 | |
39 | 39 | if (nvgpu_flcn_clear_halt_intr_status(&g->sec2_flcn, timeout)) | |
40 | nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER); | 40 | status = -EBUSY; |
41 | do { | 41 | |
42 | gk20a_writel(g, psec_falcon_irqsclr_r(), | 42 | return status; |
43 | gk20a_readl(g, psec_falcon_irqsclr_r()) | (0x10)); | ||
44 | data = gk20a_readl(g, psec_falcon_irqstat_r()); | ||
45 | if ((data & psec_falcon_irqstat_halt_true_f()) != | ||
46 | psec_falcon_irqstat_halt_true_f()) | ||
47 | /*halt irq is clear*/ | ||
48 | break; | ||
49 | nvgpu_udelay(1); | ||
50 | } while (!nvgpu_timeout_expired(&to)); | ||
51 | |||
52 | if (nvgpu_timeout_peek_expired(&to)) | ||
53 | return -EBUSY; | ||
54 | return 0; | ||
55 | } | 43 | } |
56 | 44 | ||
57 | int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) | 45 | int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 3079c79e..ca61ae46 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h | |||
@@ -129,6 +129,7 @@ struct nvgpu_falcon_engine_dependency_ops { | |||
129 | struct nvgpu_falcon_ops { | 129 | struct nvgpu_falcon_ops { |
130 | int (*reset)(struct nvgpu_falcon *flcn); | 130 | int (*reset)(struct nvgpu_falcon *flcn); |
131 | void (*set_irq)(struct nvgpu_falcon *flcn, bool enable); | 131 | void (*set_irq)(struct nvgpu_falcon *flcn, bool enable); |
132 | bool (*clear_halt_interrupt_status)(struct nvgpu_falcon *flcn); | ||
132 | bool (*is_falcon_cpu_halted)(struct nvgpu_falcon *flcn); | 133 | bool (*is_falcon_cpu_halted)(struct nvgpu_falcon *flcn); |
133 | bool (*is_falcon_idle)(struct nvgpu_falcon *flcn); | 134 | bool (*is_falcon_idle)(struct nvgpu_falcon *flcn); |
134 | bool (*is_falcon_scrubbing_done)(struct nvgpu_falcon *flcn); | 135 | bool (*is_falcon_scrubbing_done)(struct nvgpu_falcon *flcn); |
@@ -167,6 +168,8 @@ struct nvgpu_falcon { | |||
167 | 168 | ||
168 | int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn); | 169 | int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn); |
169 | int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout); | 170 | int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout); |
171 | int nvgpu_flcn_clear_halt_intr_status(struct nvgpu_falcon *flcn, | ||
172 | unsigned int timeout); | ||
170 | int nvgpu_flcn_reset(struct nvgpu_falcon *flcn); | 173 | int nvgpu_flcn_reset(struct nvgpu_falcon *flcn); |
171 | void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable, | 174 | void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable, |
172 | u32 intr_mask, u32 intr_dest); | 175 | u32 intr_mask, u32 intr_dest); |