diff options
author | Richard Zhao <rizhao@nvidia.com> | 2018-01-31 18:19:26 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-02-27 17:30:05 -0500 |
commit | 2ac0c3524530fbf34925113d93e8069f5f281fdb (patch) | |
tree | 91191c0a2cbcadc8ed71eb263e773e38ef3059ea /drivers/gpu | |
parent | c45462288d09955b2a163274d501c4d0aa10a74b (diff) |
gpu: nvgpu: vgpu: remove vgpu_locked_gmmu_map()
The function is not used anymore.
Change-Id: Iad99811e2d356362d16b961464729f5169c36f28
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649937
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c | 85 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 1 |
3 files changed, 0 insertions, 101 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c index bc0fe575..d2cb4442 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c | |||
@@ -80,91 +80,6 @@ int vgpu_init_mm_support(struct gk20a *g) | |||
80 | return err; | 80 | return err; |
81 | } | 81 | } |
82 | 82 | ||
83 | u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, | ||
84 | u64 map_offset, | ||
85 | struct nvgpu_sgt *sgt, | ||
86 | u64 buffer_offset, | ||
87 | u64 size, | ||
88 | int pgsz_idx, | ||
89 | u8 kind_v, | ||
90 | u32 ctag_offset, | ||
91 | u32 flags, | ||
92 | int rw_flag, | ||
93 | bool clear_ctags, | ||
94 | bool sparse, | ||
95 | bool priv, | ||
96 | struct vm_gk20a_mapping_batch *batch, | ||
97 | enum nvgpu_aperture aperture) | ||
98 | { | ||
99 | int err = 0; | ||
100 | struct device *d = dev_from_vm(vm); | ||
101 | struct gk20a *g = gk20a_from_vm(vm); | ||
102 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(d); | ||
103 | struct tegra_vgpu_cmd_msg msg; | ||
104 | struct tegra_vgpu_as_map_params *p = &msg.params.as_map; | ||
105 | u64 addr = nvgpu_sgt_get_gpu_addr(g, sgt, sgt->sgl, NULL); | ||
106 | u8 prot; | ||
107 | |||
108 | gk20a_dbg_fn(""); | ||
109 | |||
110 | /* Allocate (or validate when map_offset != 0) the virtual address. */ | ||
111 | if (!map_offset) { | ||
112 | map_offset = __nvgpu_vm_alloc_va(vm, size, | ||
113 | pgsz_idx); | ||
114 | if (!map_offset) { | ||
115 | nvgpu_err(g, "failed to allocate va space"); | ||
116 | err = -ENOMEM; | ||
117 | goto fail; | ||
118 | } | ||
119 | } | ||
120 | |||
121 | if (rw_flag == gk20a_mem_flag_read_only) | ||
122 | prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; | ||
123 | else if (rw_flag == gk20a_mem_flag_write_only) | ||
124 | prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; | ||
125 | else | ||
126 | prot = TEGRA_VGPU_MAP_PROT_NONE; | ||
127 | |||
128 | msg.cmd = TEGRA_VGPU_CMD_AS_MAP; | ||
129 | msg.handle = vgpu_get_handle(g); | ||
130 | p->handle = vm->handle; | ||
131 | p->addr = addr; | ||
132 | p->gpu_va = map_offset; | ||
133 | p->size = size; | ||
134 | if (pgsz_idx == gmmu_page_size_kernel) { | ||
135 | u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; | ||
136 | |||
137 | if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) { | ||
138 | pgsz_idx = gmmu_page_size_small; | ||
139 | } else if (page_size == | ||
140 | vm->gmmu_page_sizes[gmmu_page_size_big]) { | ||
141 | pgsz_idx = gmmu_page_size_big; | ||
142 | } else { | ||
143 | nvgpu_err(g, "invalid kernel page size %d", | ||
144 | page_size); | ||
145 | goto fail; | ||
146 | } | ||
147 | } | ||
148 | p->pgsz_idx = pgsz_idx; | ||
149 | p->iova = mapping ? 1 : 0; | ||
150 | p->kind = kind_v; | ||
151 | p->cacheable = (flags & NVGPU_VM_MAP_CACHEABLE) ? 1 : 0; | ||
152 | p->prot = prot; | ||
153 | p->ctag_offset = ctag_offset; | ||
154 | p->clear_ctags = clear_ctags; | ||
155 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
156 | err = err ? err : msg.ret; | ||
157 | if (err) | ||
158 | goto fail; | ||
159 | |||
160 | /* TLB invalidate handled on server side */ | ||
161 | |||
162 | return map_offset; | ||
163 | fail: | ||
164 | nvgpu_err(g, "%s: failed with err=%d", __func__, err); | ||
165 | return 0; | ||
166 | } | ||
167 | |||
168 | void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, | 83 | void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, |
169 | u64 vaddr, | 84 | u64 vaddr, |
170 | u64 size, | 85 | u64 size, |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h index eee54779..bb38fa27 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h | |||
@@ -17,21 +17,6 @@ | |||
17 | #ifndef _MM_VGPU_H_ | 17 | #ifndef _MM_VGPU_H_ |
18 | #define _MM_VGPU_H_ | 18 | #define _MM_VGPU_H_ |
19 | 19 | ||
20 | u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, | ||
21 | u64 map_offset, | ||
22 | struct nvgpu_sgt *sgt, | ||
23 | u64 buffer_offset, | ||
24 | u64 size, | ||
25 | int pgsz_idx, | ||
26 | u8 kind_v, | ||
27 | u32 ctag_offset, | ||
28 | u32 flags, | ||
29 | int rw_flag, | ||
30 | bool clear_ctags, | ||
31 | bool sparse, | ||
32 | bool priv, | ||
33 | struct vm_gk20a_mapping_batch *batch, | ||
34 | enum nvgpu_aperture aperture); | ||
35 | void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, | 20 | void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, |
36 | u64 vaddr, | 21 | u64 vaddr, |
37 | u64 size, | 22 | u64 size, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 78d64ebb..ae32a406 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -50,7 +50,6 @@ enum { | |||
50 | TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7, | 50 | TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7, |
51 | TEGRA_VGPU_CMD_AS_BIND_SHARE = 8, | 51 | TEGRA_VGPU_CMD_AS_BIND_SHARE = 8, |
52 | TEGRA_VGPU_CMD_AS_FREE_SHARE = 9, | 52 | TEGRA_VGPU_CMD_AS_FREE_SHARE = 9, |
53 | TEGRA_VGPU_CMD_AS_MAP = 10, | ||
54 | TEGRA_VGPU_CMD_AS_UNMAP = 11, | 53 | TEGRA_VGPU_CMD_AS_UNMAP = 11, |
55 | TEGRA_VGPU_CMD_CHANNEL_BIND = 13, | 54 | TEGRA_VGPU_CMD_CHANNEL_BIND = 13, |
56 | TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14, | 55 | TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14, |