diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-02 18:39:27 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 06:06:59 -0400 |
commit | 29b688960fcf6279f58d95f7e17f31ef15129a80 (patch) | |
tree | 38d90b161b404c2b7884c6d40d35b9e858fe8960 /drivers/gpu | |
parent | 0e2e3898f7f8828ff9601d414f730b9fa8d09b3f (diff) |
gpu: nvgpu: add suspend_all_sms gr ops
This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: Icdae3b6ed67a3d3deeb17f29528184b2d7a70af5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512215
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 4 |
5 files changed, 13 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index f97534b5..f94be010 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -373,6 +373,8 @@ struct gpu_ops { | |||
373 | void (*suspend_single_sm)(struct gk20a *g, | 373 | void (*suspend_single_sm)(struct gk20a *g, |
374 | u32 gpc, u32 tpc, u32 sm, | 374 | u32 gpc, u32 tpc, u32 sm, |
375 | u32 global_esr_mask, bool check_errors); | 375 | u32 global_esr_mask, bool check_errors); |
376 | void (*suspend_all_sms)(struct gk20a *g, | ||
377 | u32 global_esr_mask, bool check_errors); | ||
376 | } gr; | 378 | } gr; |
377 | struct { | 379 | struct { |
378 | void (*init_hw)(struct gk20a *g); | 380 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 64b991a2..f6857b66 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1147,7 +1147,7 @@ void gr_gk20a_init_sm_id_table(struct gk20a *g) | |||
1147 | * Return number of TPCs in a GPC | 1147 | * Return number of TPCs in a GPC |
1148 | * Return 0 if GPC index is invalid i.e. GPC is disabled | 1148 | * Return 0 if GPC index is invalid i.e. GPC is disabled |
1149 | */ | 1149 | */ |
1150 | static u32 gr_gk20a_get_tpc_count(struct gr_gk20a *gr, u32 gpc_index) | 1150 | u32 gr_gk20a_get_tpc_count(struct gr_gk20a *gr, u32 gpc_index) |
1151 | { | 1151 | { |
1152 | if (gpc_index >= gr->gpc_count) | 1152 | if (gpc_index >= gr->gpc_count) |
1153 | return 0; | 1153 | return 0; |
@@ -8047,7 +8047,7 @@ void gk20a_gr_suspend_single_sm(struct gk20a *g, | |||
8047 | } | 8047 | } |
8048 | } | 8048 | } |
8049 | 8049 | ||
8050 | void gk20a_suspend_all_sms(struct gk20a *g, | 8050 | void gk20a_gr_suspend_all_sms(struct gk20a *g, |
8051 | u32 global_esr_mask, bool check_errors) | 8051 | u32 global_esr_mask, bool check_errors) |
8052 | { | 8052 | { |
8053 | struct gr_gk20a *gr = &g->gr; | 8053 | struct gr_gk20a *gr = &g->gr; |
@@ -8062,8 +8062,10 @@ void gk20a_suspend_all_sms(struct gk20a *g, | |||
8062 | return; | 8062 | return; |
8063 | } | 8063 | } |
8064 | 8064 | ||
8065 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "suspending all sms"); | ||
8065 | /* assert stop trigger. uniformity assumption: all SMs will have | 8066 | /* assert stop trigger. uniformity assumption: all SMs will have |
8066 | * the same state in dbg_control0. */ | 8067 | * the same state in dbg_control0. |
8068 | */ | ||
8067 | dbgr_control0 = | 8069 | dbgr_control0 = |
8068 | gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r()); | 8070 | gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r()); |
8069 | dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(); | 8071 | dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(); |
@@ -8221,7 +8223,7 @@ bool gr_gk20a_suspend_context(struct channel_gk20a *ch) | |||
8221 | bool ctx_resident = false; | 8223 | bool ctx_resident = false; |
8222 | 8224 | ||
8223 | if (gk20a_is_channel_ctx_resident(ch)) { | 8225 | if (gk20a_is_channel_ctx_resident(ch)) { |
8224 | gk20a_suspend_all_sms(g, 0, false); | 8226 | g->ops.gr.suspend_all_sms(g, 0, false); |
8225 | ctx_resident = true; | 8227 | ctx_resident = true; |
8226 | } else { | 8228 | } else { |
8227 | gk20a_disable_channel_tsg(g, ch); | 8229 | gk20a_disable_channel_tsg(g, ch); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index a9b7c2d7..90abcf22 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -618,8 +618,9 @@ void gk20a_resume_all_sms(struct gk20a *g); | |||
618 | void gk20a_gr_suspend_single_sm(struct gk20a *g, | 618 | void gk20a_gr_suspend_single_sm(struct gk20a *g, |
619 | u32 gpc, u32 tpc, u32 sm, | 619 | u32 gpc, u32 tpc, u32 sm, |
620 | u32 global_esr_mask, bool check_errors); | 620 | u32 global_esr_mask, bool check_errors); |
621 | void gk20a_suspend_all_sms(struct gk20a *g, | 621 | void gk20a_gr_suspend_all_sms(struct gk20a *g, |
622 | u32 global_esr_mask, bool check_errors); | 622 | u32 global_esr_mask, bool check_errors); |
623 | u32 gr_gk20a_get_tpc_count(struct gr_gk20a *gr, u32 gpc_index); | ||
623 | int gk20a_gr_lock_down_sm(struct gk20a *g, | 624 | int gk20a_gr_lock_down_sm(struct gk20a *g, |
624 | u32 gpc, u32 tpc, u32 global_esr_mask, | 625 | u32 gpc, u32 tpc, u32 global_esr_mask, |
625 | bool check_errors); | 626 | bool check_errors); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index d985a44d..4cabf214 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1632,4 +1632,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1632 | gops->gr.get_esr_sm_sel = gk20a_gr_get_esr_sm_sel; | 1632 | gops->gr.get_esr_sm_sel = gk20a_gr_get_esr_sm_sel; |
1633 | gops->gr.sm_debugger_attached = gk20a_gr_sm_debugger_attached; | 1633 | gops->gr.sm_debugger_attached = gk20a_gr_sm_debugger_attached; |
1634 | gops->gr.suspend_single_sm = gk20a_gr_suspend_single_sm; | 1634 | gops->gr.suspend_single_sm = gk20a_gr_suspend_single_sm; |
1635 | gops->gr.suspend_all_sms = gk20a_gr_suspend_all_sms; | ||
1635 | } | 1636 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 5d17472f..afd3750b 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1822,7 +1822,7 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, | |||
1822 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1822 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1823 | "CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n", | 1823 | "CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n", |
1824 | gpc, tpc); | 1824 | gpc, tpc); |
1825 | gk20a_suspend_all_sms(g, global_mask, false); | 1825 | g->ops.gr.suspend_all_sms(g, global_mask, false); |
1826 | 1826 | ||
1827 | gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch); | 1827 | gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch); |
1828 | } else { | 1828 | } else { |
@@ -1991,7 +1991,7 @@ static bool gr_gp10b_suspend_context(struct channel_gk20a *ch, | |||
1991 | *cilp_preempt_pending = false; | 1991 | *cilp_preempt_pending = false; |
1992 | 1992 | ||
1993 | if (gk20a_is_channel_ctx_resident(ch)) { | 1993 | if (gk20a_is_channel_ctx_resident(ch)) { |
1994 | gk20a_suspend_all_sms(g, 0, false); | 1994 | g->ops.gr.suspend_all_sms(g, 0, false); |
1995 | 1995 | ||
1996 | if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) { | 1996 | if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) { |
1997 | err = gr_gp10b_set_cilp_preempt_pending(g, ch); | 1997 | err = gr_gp10b_set_cilp_preempt_pending(g, ch); |