gpu: nvgpu: remove unused regops HALs

Below regops HALs are not being called from anywhere, so remove them
gops.regops.get_runcontrol_whitelist_ranges()
gops.regops.get_runcontrol_whitelist_ranges_count()
gops.regops.get_qctl_whitelist_ranges()
gops.regops.get_qctl_whitelist_ranges_count()

HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it
was originally only needed for gk20a which is not unsupported
So remove this HAL and its call too

Jira NVGPU-620

Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813106
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

14 files changed, 0 insertions, 268 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index fac7c5df..4d4b4cb1 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1140,15 +1140,8 @@ struct gpu_ops {
                 u64 (*get_context_whitelist_ranges_count)(void);
                 const u32* (*get_runcontrol_whitelist)(void);
                 u64 (*get_runcontrol_whitelist_count)(void);
-                const struct regop_offset_range* (
-                                *get_runcontrol_whitelist_ranges)(void);
-                u64 (*get_runcontrol_whitelist_ranges_count)(void);
                 const u32* (*get_qctl_whitelist)(void);
                 u64 (*get_qctl_whitelist_count)(void);
-                const struct regop_offset_range* (
-                                *get_qctl_whitelist_ranges)(void);
-                u64 (*get_qctl_whitelist_ranges_count)(void);
-                int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s);
         } regops;
         struct {
                 void (*intr_mask)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 2f90512e..ca7081cf 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -574,16 +574,8 @@ static const struct gpu_ops gm20b_ops = {
                 .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist,
                 .get_runcontrol_whitelist_count =
                         gm20b_get_runcontrol_whitelist_count,
-                .get_runcontrol_whitelist_ranges =
-                        gm20b_get_runcontrol_whitelist_ranges,
-                .get_runcontrol_whitelist_ranges_count =
-                        gm20b_get_runcontrol_whitelist_ranges_count,
                 .get_qctl_whitelist = gm20b_get_qctl_whitelist,
                 .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count,
-                .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges,
-                .get_qctl_whitelist_ranges_count =
-                        gm20b_get_qctl_whitelist_ranges_count,
-                .apply_smpc_war = gm20b_apply_smpc_war,
         },
         .mc = {
                 .intr_mask = mc_gk20a_intr_mask,
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
index e23a0a62..ab865b68 100644
--- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
@@ -23,12 +23,9 @@
  */
 
 #include "gk20a/gk20a.h"
-#include "gk20a/dbg_gpu_gk20a.h"
 #include "gk20a/regops_gk20a.h"
 #include "regops_gm20b.h"
 
-#include <nvgpu/bsearch.h>
-
 static const struct regop_offset_range gm20b_global_whitelist_ranges[] = {
         { 0x00001a00,   3 },
         { 0x0000259c,   1 },
@@ -366,29 +363,12 @@ static const u32 gm20b_runcontrol_whitelist[] = {
 static const u64 gm20b_runcontrol_whitelist_count =
         ARRAY_SIZE(gm20b_runcontrol_whitelist);
 
-static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = {
-        { 0x00419e10,   1 },
-        { 0x0041c610,   1 },
-        { 0x0041ce10,   1 },
-        { 0x00501e10,   1 },
-        { 0x00504610,   1 },
-        { 0x00504e10,   1 },
-};
-static const u64 gm20b_runcontrol_whitelist_ranges_count =
-        ARRAY_SIZE(gm20b_runcontrol_whitelist_ranges);
-
-
 /* quad ctl */
 static const u32 gm20b_qctl_whitelist[] = {
 };
 static const u64 gm20b_qctl_whitelist_count =
         ARRAY_SIZE(gm20b_qctl_whitelist);
 
-static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = {
-};
-static const u64 gm20b_qctl_whitelist_ranges_count =
-        ARRAY_SIZE(gm20b_qctl_whitelist_ranges);
-
 const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void)
 {
         return gm20b_global_whitelist_ranges;
@@ -419,16 +399,6 @@ u64 gm20b_get_runcontrol_whitelist_count(void)
         return gm20b_runcontrol_whitelist_count;
 }
 
-const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void)
-{
-        return gm20b_runcontrol_whitelist_ranges;
-}
-
-u64 gm20b_get_runcontrol_whitelist_ranges_count(void)
-{
-        return gm20b_runcontrol_whitelist_ranges_count;
-}
-
 const u32 *gm20b_get_qctl_whitelist(void)
 {
         return gm20b_qctl_whitelist;
@@ -438,19 +408,3 @@ u64 gm20b_get_qctl_whitelist_count(void)
 {
         return gm20b_qctl_whitelist_count;
 }
-
-const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void)
-{
-        return gm20b_qctl_whitelist_ranges;
-}
-
-u64 gm20b_get_qctl_whitelist_ranges_count(void)
-{
-        return gm20b_qctl_whitelist_ranges_count;
-}
-
-int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
-{
-        /* Not needed on gm20b */
-        return 0;
-}
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 3408cdfa..da1a44a9 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -701,16 +701,8 @@ static const struct gpu_ops gp106_ops = {
                 .get_runcontrol_whitelist = gp106_get_runcontrol_whitelist,
                 .get_runcontrol_whitelist_count =
                         gp106_get_runcontrol_whitelist_count,
-                .get_runcontrol_whitelist_ranges =
-                        gp106_get_runcontrol_whitelist_ranges,
-                .get_runcontrol_whitelist_ranges_count =
-                        gp106_get_runcontrol_whitelist_ranges_count,
                 .get_qctl_whitelist = gp106_get_qctl_whitelist,
                 .get_qctl_whitelist_count = gp106_get_qctl_whitelist_count,
-                .get_qctl_whitelist_ranges = gp106_get_qctl_whitelist_ranges,
-                .get_qctl_whitelist_ranges_count =
-                        gp106_get_qctl_whitelist_ranges_count,
-                .apply_smpc_war = gp106_apply_smpc_war,
         },
         .mc = {
                 .intr_mask = mc_gp10b_intr_mask,
diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.c b/drivers/gpu/nvgpu/gp106/regops_gp106.c
index 25b88eeb..581b280d 100644
--- a/drivers/gpu/nvgpu/gp106/regops_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/regops_gp106.c
@@ -23,12 +23,9 @@
  */
 
 #include "gk20a/gk20a.h"
-#include "gk20a/dbg_gpu_gk20a.h"
 #include "gk20a/regops_gk20a.h"
 #include "regops_gp106.h"
 
-#include <nvgpu/bsearch.h>
-
 static const struct regop_offset_range gp106_global_whitelist_ranges[] = {
         { 0x000004f0,   1},
         { 0x00001a00,   3},
@@ -1697,23 +1694,12 @@ static const u32 gp106_runcontrol_whitelist[] = {
 static const u64 gp106_runcontrol_whitelist_count =
         ARRAY_SIZE(gp106_runcontrol_whitelist);
 
-static const struct regop_offset_range gp106_runcontrol_whitelist_ranges[] = {
-};
-static const u64 gp106_runcontrol_whitelist_ranges_count =
-        ARRAY_SIZE(gp106_runcontrol_whitelist_ranges);
-
-
 /* quad ctl */
 static const u32 gp106_qctl_whitelist[] = {
 };
 static const u64 gp106_qctl_whitelist_count =
         ARRAY_SIZE(gp106_qctl_whitelist);
 
-static const struct regop_offset_range gp106_qctl_whitelist_ranges[] = {
-};
-static const u64 gp106_qctl_whitelist_ranges_count =
-        ARRAY_SIZE(gp106_qctl_whitelist_ranges);
-
 const struct regop_offset_range *gp106_get_global_whitelist_ranges(void)
 {
         return gp106_global_whitelist_ranges;
@@ -1744,16 +1730,6 @@ u64 gp106_get_runcontrol_whitelist_count(void)
         return gp106_runcontrol_whitelist_count;
 }
 
-const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void)
-{
-        return gp106_runcontrol_whitelist_ranges;
-}
-
-u64 gp106_get_runcontrol_whitelist_ranges_count(void)
-{
-        return gp106_runcontrol_whitelist_ranges_count;
-}
-
 const u32 *gp106_get_qctl_whitelist(void)
 {
         return gp106_qctl_whitelist;
@@ -1763,19 +1739,3 @@ u64 gp106_get_qctl_whitelist_count(void)
 {
         return gp106_qctl_whitelist_count;
 }
-
-const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void)
-{
-        return gp106_qctl_whitelist_ranges;
-}
-
-u64 gp106_get_qctl_whitelist_ranges_count(void)
-{
-        return gp106_qctl_whitelist_ranges_count;
-}
-
-int gp106_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
-{
-        /* Not needed on gp106 */
-        return 0;
-}
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 321a89fd..af64d2a9 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -626,16 +626,8 @@ static const struct gpu_ops gp10b_ops = {
                 .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist,
                 .get_runcontrol_whitelist_count =
                         gp10b_get_runcontrol_whitelist_count,
-                .get_runcontrol_whitelist_ranges =
-                        gp10b_get_runcontrol_whitelist_ranges,
-                .get_runcontrol_whitelist_ranges_count =
-                        gp10b_get_runcontrol_whitelist_ranges_count,
                 .get_qctl_whitelist = gp10b_get_qctl_whitelist,
                 .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
-                .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges,
-                .get_qctl_whitelist_ranges_count =
-                        gp10b_get_qctl_whitelist_ranges_count,
-                .apply_smpc_war = gp10b_apply_smpc_war,
         },
         .mc = {
                 .intr_mask = mc_gp10b_intr_mask,
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
index 8113f7d5..c61709e0 100644
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
@@ -23,12 +23,9 @@
  */
 
 #include "gk20a/gk20a.h"
-#include "gk20a/dbg_gpu_gk20a.h"
 #include "gk20a/regops_gk20a.h"
 #include "regops_gp10b.h"
 
-#include <nvgpu/bsearch.h>
-
 static const struct regop_offset_range gp10b_global_whitelist_ranges[] = {
         { 0x000004f0,   1},
         { 0x00001a00,   3},
@@ -393,23 +390,12 @@ static const u32 gp10b_runcontrol_whitelist[] = {
 static const u64 gp10b_runcontrol_whitelist_count =
         ARRAY_SIZE(gp10b_runcontrol_whitelist);
 
-static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = {
-};
-static const u64 gp10b_runcontrol_whitelist_ranges_count =
-        ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges);
-
-
 /* quad ctl */
 static const u32 gp10b_qctl_whitelist[] = {
 };
 static const u64 gp10b_qctl_whitelist_count =
         ARRAY_SIZE(gp10b_qctl_whitelist);
 
-static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = {
-};
-static const u64 gp10b_qctl_whitelist_ranges_count =
-        ARRAY_SIZE(gp10b_qctl_whitelist_ranges);
-
 const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
 {
         return gp10b_global_whitelist_ranges;
@@ -440,16 +426,6 @@ u64 gp10b_get_runcontrol_whitelist_count(void)
         return gp10b_runcontrol_whitelist_count;
 }
 
-const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void)
-{
-        return gp10b_runcontrol_whitelist_ranges;
-}
-
-u64 gp10b_get_runcontrol_whitelist_ranges_count(void)
-{
-        return gp10b_runcontrol_whitelist_ranges_count;
-}
-
 const u32 *gp10b_get_qctl_whitelist(void)
 {
         return gp10b_qctl_whitelist;
@@ -459,19 +435,3 @@ u64 gp10b_get_qctl_whitelist_count(void)
 {
         return gp10b_qctl_whitelist_count;
 }
-
-const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void)
-{
-        return gp10b_qctl_whitelist_ranges;
-}
-
-u64 gp10b_get_qctl_whitelist_ranges_count(void)
-{
-        return gp10b_qctl_whitelist_ranges_count;
-}
-
-int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
-{
-        /* Not needed on gp10b */
-        return 0;
-}
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 1bc5d091..9d90d1d4 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -790,16 +790,8 @@ static const struct gpu_ops gv100_ops = {
                 .get_runcontrol_whitelist = gv100_get_runcontrol_whitelist,
                 .get_runcontrol_whitelist_count =
                         gv100_get_runcontrol_whitelist_count,
-                .get_runcontrol_whitelist_ranges =
-                        gv100_get_runcontrol_whitelist_ranges,
-                .get_runcontrol_whitelist_ranges_count =
-                        gv100_get_runcontrol_whitelist_ranges_count,
                 .get_qctl_whitelist = gv100_get_qctl_whitelist,
                 .get_qctl_whitelist_count = gv100_get_qctl_whitelist_count,
-                .get_qctl_whitelist_ranges = gv100_get_qctl_whitelist_ranges,
-                .get_qctl_whitelist_ranges_count =
-                        gv100_get_qctl_whitelist_ranges_count,
-                .apply_smpc_war = gv100_apply_smpc_war,
         },
         .mc = {
                 .intr_mask = mc_gp10b_intr_mask,
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.c b/drivers/gpu/nvgpu/gv100/regops_gv100.c
index c6ce6b94..baf57c78 100644
--- a/drivers/gpu/nvgpu/gv100/regops_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/regops_gv100.c
@@ -23,7 +23,6 @@
  */
 
 #include "gk20a/gk20a.h"
-#include "gk20a/dbg_gpu_gk20a.h"
 #include "gk20a/regops_gk20a.h"
 #include "regops_gv100.h"
 
@@ -5626,19 +5625,12 @@ static const struct regop_offset_range gv100_global_whitelist_ranges[] = {
 static const u64 gv100_global_whitelist_ranges_count =
         ARRAY_SIZE(gv100_global_whitelist_ranges);
 
-/* context */
-
 /* runcontrol */
 static const u32 gv100_runcontrol_whitelist[] = {
 };
 static const u64 gv100_runcontrol_whitelist_count =
         ARRAY_SIZE(gv100_runcontrol_whitelist);
 
-static const struct regop_offset_range gv100_runcontrol_whitelist_ranges[] = {
-};
-static const u64 gv100_runcontrol_whitelist_ranges_count =
-        ARRAY_SIZE(gv100_runcontrol_whitelist_ranges);
-
 
 /* quad ctl */
 static const u32 gv100_qctl_whitelist[] = {
@@ -5646,11 +5638,6 @@ static const u32 gv100_qctl_whitelist[] = {
 static const u64 gv100_qctl_whitelist_count =
         ARRAY_SIZE(gv100_qctl_whitelist);
 
-static const struct regop_offset_range gv100_qctl_whitelist_ranges[] = {
-};
-static const u64 gv100_qctl_whitelist_ranges_count =
-        ARRAY_SIZE(gv100_qctl_whitelist_ranges);
-
 const struct regop_offset_range *gv100_get_global_whitelist_ranges(void)
 {
         return gv100_global_whitelist_ranges;
@@ -5681,16 +5668,6 @@ u64 gv100_get_runcontrol_whitelist_count(void)
         return gv100_runcontrol_whitelist_count;
 }
 
-const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void)
-{
-        return gv100_runcontrol_whitelist_ranges;
-}
-
-u64 gv100_get_runcontrol_whitelist_ranges_count(void)
-{
-        return gv100_runcontrol_whitelist_ranges_count;
-}
-
 const u32 *gv100_get_qctl_whitelist(void)
 {
         return gv100_qctl_whitelist;
@@ -5700,19 +5677,3 @@ u64 gv100_get_qctl_whitelist_count(void)
 {
         return gv100_qctl_whitelist_count;
 }
-
-const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void)
-{
-        return gv100_qctl_whitelist_ranges;
-}
-
-u64 gv100_get_qctl_whitelist_ranges_count(void)
-{
-        return gv100_qctl_whitelist_ranges_count;
-}
-
-int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
-{
-        /* Not needed on gv100 */
-        return 0;
-}
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index e5d7e632..a27d9ab5 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -722,16 +722,8 @@ static const struct gpu_ops gv11b_ops = {
                 .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist,
                 .get_runcontrol_whitelist_count =
                         gv11b_get_runcontrol_whitelist_count,
-                .get_runcontrol_whitelist_ranges =
-                        gv11b_get_runcontrol_whitelist_ranges,
-                .get_runcontrol_whitelist_ranges_count =
-                        gv11b_get_runcontrol_whitelist_ranges_count,
                 .get_qctl_whitelist = gv11b_get_qctl_whitelist,
                 .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
-                .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges,
-                .get_qctl_whitelist_ranges_count =
-                        gv11b_get_qctl_whitelist_ranges_count,
-                .apply_smpc_war = gv11b_apply_smpc_war,
         },
         .mc = {
                 .intr_mask = mc_gp10b_intr_mask,
diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c
index 768674fe..0bc8ab05 100644
--- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c
@@ -23,7 +23,6 @@
  */
 
 #include "gk20a/gk20a.h"
-#include "gk20a/dbg_gpu_gk20a.h"
 #include "gk20a/regops_gk20a.h"
 #include "regops_gv11b.h"
 
@@ -1452,23 +1451,12 @@ static const u32 gv11b_runcontrol_whitelist[] = {
 static const u64 gv11b_runcontrol_whitelist_count =
         ARRAY_SIZE(gv11b_runcontrol_whitelist);
 
-static const struct regop_offset_range gv11b_runcontrol_whitelist_ranges[] = {
-};
-static const u64 gv11b_runcontrol_whitelist_ranges_count =
-        ARRAY_SIZE(gv11b_runcontrol_whitelist_ranges);
-
-
 /* quad ctl */
 static const u32 gv11b_qctl_whitelist[] = {
 };
 static const u64 gv11b_qctl_whitelist_count =
         ARRAY_SIZE(gv11b_qctl_whitelist);
 
-static const struct regop_offset_range gv11b_qctl_whitelist_ranges[] = {
-};
-static const u64 gv11b_qctl_whitelist_ranges_count =
-        ARRAY_SIZE(gv11b_qctl_whitelist_ranges);
-
 const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void)
 {
         return gv11b_global_whitelist_ranges;
@@ -1499,16 +1487,6 @@ u64 gv11b_get_runcontrol_whitelist_count(void)
         return gv11b_runcontrol_whitelist_count;
 }
 
-const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void)
-{
-        return gv11b_runcontrol_whitelist_ranges;
-}
-
-u64 gv11b_get_runcontrol_whitelist_ranges_count(void)
-{
-        return gv11b_runcontrol_whitelist_ranges_count;
-}
-
 const u32 *gv11b_get_qctl_whitelist(void)
 {
         return gv11b_qctl_whitelist;
@@ -1518,19 +1496,3 @@ u64 gv11b_get_qctl_whitelist_count(void)
 {
         return gv11b_qctl_whitelist_count;
 }
-
-const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void)
-{
-        return gv11b_qctl_whitelist_ranges;
-}
-
-u64 gv11b_get_qctl_whitelist_ranges_count(void)
-{
-        return gv11b_qctl_whitelist_ranges_count;
-}
-
-int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
-{
-        /* Not needed on gv11b */
-        return 0;
-}
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
index e4e7394e..9ea681b1 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
@@ -1053,10 +1053,8 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
         if (err) {
                 nvgpu_err(g,
                           "error (%d) during smpc ctxsw mode update", err);
-                goto clean_up;
         }
 
-        err = g->ops.regops.apply_smpc_war(dbg_s);
  clean_up:
         nvgpu_mutex_release(&g->dbg_sessions_lock);
         gk20a_idle(g);
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 0b6a5cb5..58f595f4 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -466,16 +466,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist,
                 .get_runcontrol_whitelist_count =
                         gp10b_get_runcontrol_whitelist_count,
-                .get_runcontrol_whitelist_ranges =
-                        gp10b_get_runcontrol_whitelist_ranges,
-                .get_runcontrol_whitelist_ranges_count =
-                        gp10b_get_runcontrol_whitelist_ranges_count,
                 .get_qctl_whitelist = gp10b_get_qctl_whitelist,
                 .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
-                .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges,
-                .get_qctl_whitelist_ranges_count =
-                        gp10b_get_qctl_whitelist_ranges_count,
-                .apply_smpc_war = gp10b_apply_smpc_war,
         },
         .mc = {
                 .intr_mask = NULL,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 85835cee..9832a714 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -535,16 +535,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist,
                 .get_runcontrol_whitelist_count =
                         gv11b_get_runcontrol_whitelist_count,
-                .get_runcontrol_whitelist_ranges =
-                        gv11b_get_runcontrol_whitelist_ranges,
-                .get_runcontrol_whitelist_ranges_count =
-                        gv11b_get_runcontrol_whitelist_ranges_count,
                 .get_qctl_whitelist = gv11b_get_qctl_whitelist,
                 .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
-                .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges,
-                .get_qctl_whitelist_ranges_count =
-                        gv11b_get_qctl_whitelist_ranges_count,
-                .apply_smpc_war = gv11b_apply_smpc_war,
         },
         .mc = {
                 .intr_mask = NULL,