diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2018-02-12 13:00:32 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-02-26 00:48:15 -0500 |
commit | 223ea4d8a179835dd5899bbc12fe78b4998b0bd7 (patch) | |
tree | 9ba243761bd37e7467f0501416f40f2ab7319b84 /drivers/gpu | |
parent | b5d3cf444eeeb62a593365532b22e44f9360a484 (diff) |
gpu: nvgpu: gv100: update registers
Update GV100 registers for nvlink.
JIRA EVLR-2328
Change-Id: I0fad01560022d979fbdcd94fd066e507691969ae
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1656052
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
13 files changed, 4716 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h index a4fcd1e6..1bac1a6a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -60,6 +60,82 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void) | |||
60 | { | 60 | { |
61 | return 0x00100800U; | 61 | return 0x00100800U; |
62 | } | 62 | } |
63 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_f(u32 v) | ||
64 | { | ||
65 | return (v & 0xffU) << 16U; | ||
66 | } | ||
67 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_m(void) | ||
68 | { | ||
69 | return 0xffU << 16U; | ||
70 | } | ||
71 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_v(u32 r) | ||
72 | { | ||
73 | return (r >> 16U) & 0xffU; | ||
74 | } | ||
75 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i) | ||
76 | { | ||
77 | return (v & 0x1U) << (16U + i*1U); | ||
78 | } | ||
79 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_m(u32 i) | ||
80 | { | ||
81 | return 0x1U << (16U + i*1U); | ||
82 | } | ||
83 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i) | ||
84 | { | ||
85 | return (r >> (16U + i*1U)) & 0x1U; | ||
86 | } | ||
87 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v(void) | ||
88 | { | ||
89 | return 0x00000008U; | ||
90 | } | ||
91 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i) | ||
92 | { | ||
93 | return 0x0U << (32U + i*1U); | ||
94 | } | ||
95 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v(void) | ||
96 | { | ||
97 | return 0x00000001U; | ||
98 | } | ||
99 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i) | ||
100 | { | ||
101 | return 0x1U << (32U + i*1U); | ||
102 | } | ||
103 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v(void) | ||
104 | { | ||
105 | return 0x00000000U; | ||
106 | } | ||
107 | static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i) | ||
108 | { | ||
109 | return 0x0U << (32U + i*1U); | ||
110 | } | ||
111 | static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v) | ||
112 | { | ||
113 | return (v & 0x1U) << 25U; | ||
114 | } | ||
115 | static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void) | ||
116 | { | ||
117 | return 0x1U << 25U; | ||
118 | } | ||
119 | static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r) | ||
120 | { | ||
121 | return (r >> 25U) & 0x1U; | ||
122 | } | ||
123 | static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void) | ||
124 | { | ||
125 | return 0x00000000U; | ||
126 | } | ||
127 | static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) | ||
128 | { | ||
129 | return 0x0U; | ||
130 | } | ||
131 | static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void) | ||
132 | { | ||
133 | return 0x00000001U; | ||
134 | } | ||
135 | static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) | ||
136 | { | ||
137 | return 0x2000000U; | ||
138 | } | ||
63 | static inline u32 fb_mmu_ctrl_r(void) | 139 | static inline u32 fb_mmu_ctrl_r(void) |
64 | { | 140 | { |
65 | return 0x00100c80U; | 141 | return 0x00100c80U; |
@@ -100,6 +176,178 @@ static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) | |||
100 | { | 176 | { |
101 | return 0x0U; | 177 | return 0x0U; |
102 | } | 178 | } |
179 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_f(u32 v) | ||
180 | { | ||
181 | return (v & 0x3U) << 24U; | ||
182 | } | ||
183 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void) | ||
184 | { | ||
185 | return 0x3U << 24U; | ||
186 | } | ||
187 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_v(u32 r) | ||
188 | { | ||
189 | return (r >> 24U) & 0x3U; | ||
190 | } | ||
191 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_v(void) | ||
192 | { | ||
193 | return 0x00000000U; | ||
194 | } | ||
195 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void) | ||
196 | { | ||
197 | return 0x0U; | ||
198 | } | ||
199 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_v(void) | ||
200 | { | ||
201 | return 0x00000001U; | ||
202 | } | ||
203 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_f(void) | ||
204 | { | ||
205 | return 0x1000000U; | ||
206 | } | ||
207 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_v(void) | ||
208 | { | ||
209 | return 0x00000002U; | ||
210 | } | ||
211 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void) | ||
212 | { | ||
213 | return 0x2000000U; | ||
214 | } | ||
215 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_v(void) | ||
216 | { | ||
217 | return 0x00000003U; | ||
218 | } | ||
219 | static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_f(void) | ||
220 | { | ||
221 | return 0x3000000U; | ||
222 | } | ||
223 | static inline u32 fb_hsmmu_pri_mmu_ctrl_r(void) | ||
224 | { | ||
225 | return 0x001fac80U; | ||
226 | } | ||
227 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(u32 v) | ||
228 | { | ||
229 | return (v & 0x3U) << 24U; | ||
230 | } | ||
231 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(void) | ||
232 | { | ||
233 | return 0x3U << 24U; | ||
234 | } | ||
235 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(u32 r) | ||
236 | { | ||
237 | return (r >> 24U) & 0x3U; | ||
238 | } | ||
239 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v(void) | ||
240 | { | ||
241 | return 0x00000000U; | ||
242 | } | ||
243 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_f(void) | ||
244 | { | ||
245 | return 0x0U; | ||
246 | } | ||
247 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_v(void) | ||
248 | { | ||
249 | return 0x00000001U; | ||
250 | } | ||
251 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_f(void) | ||
252 | { | ||
253 | return 0x1000000U; | ||
254 | } | ||
255 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_v(void) | ||
256 | { | ||
257 | return 0x00000002U; | ||
258 | } | ||
259 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f(void) | ||
260 | { | ||
261 | return 0x2000000U; | ||
262 | } | ||
263 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v(void) | ||
264 | { | ||
265 | return 0x00000003U; | ||
266 | } | ||
267 | static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f(void) | ||
268 | { | ||
269 | return 0x3000000U; | ||
270 | } | ||
271 | static inline u32 fb_hshub_num_active_ltcs_r(void) | ||
272 | { | ||
273 | return 0x001fbc20U; | ||
274 | } | ||
275 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_f(u32 v) | ||
276 | { | ||
277 | return (v & 0xffU) << 16U; | ||
278 | } | ||
279 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_m(void) | ||
280 | { | ||
281 | return 0xffU << 16U; | ||
282 | } | ||
283 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_v(u32 r) | ||
284 | { | ||
285 | return (r >> 16U) & 0xffU; | ||
286 | } | ||
287 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i) | ||
288 | { | ||
289 | return (v & 0x1U) << (16U + i*1U); | ||
290 | } | ||
291 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_m(u32 i) | ||
292 | { | ||
293 | return 0x1U << (16U + i*1U); | ||
294 | } | ||
295 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i) | ||
296 | { | ||
297 | return (r >> (16U + i*1U)) & 0x1U; | ||
298 | } | ||
299 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v(void) | ||
300 | { | ||
301 | return 0x00000008U; | ||
302 | } | ||
303 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i) | ||
304 | { | ||
305 | return 0x0U << (32U + i*1U); | ||
306 | } | ||
307 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v(void) | ||
308 | { | ||
309 | return 0x00000001U; | ||
310 | } | ||
311 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i) | ||
312 | { | ||
313 | return 0x1U << (32U + i*1U); | ||
314 | } | ||
315 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v(void) | ||
316 | { | ||
317 | return 0x00000000U; | ||
318 | } | ||
319 | static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i) | ||
320 | { | ||
321 | return 0x0U << (32U + i*1U); | ||
322 | } | ||
323 | static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x1U) << 25U; | ||
326 | } | ||
327 | static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void) | ||
328 | { | ||
329 | return 0x1U << 25U; | ||
330 | } | ||
331 | static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r) | ||
332 | { | ||
333 | return (r >> 25U) & 0x1U; | ||
334 | } | ||
335 | static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void) | ||
336 | { | ||
337 | return 0x00000000U; | ||
338 | } | ||
339 | static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) | ||
340 | { | ||
341 | return 0x0U; | ||
342 | } | ||
343 | static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void) | ||
344 | { | ||
345 | return 0x00000001U; | ||
346 | } | ||
347 | static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) | ||
348 | { | ||
349 | return 0x2000000U; | ||
350 | } | ||
103 | static inline u32 fb_priv_mmu_phy_secure_r(void) | 351 | static inline u32 fb_priv_mmu_phy_secure_r(void) |
104 | { | 352 | { |
105 | return 0x00100ce4U; | 353 | return 0x00100ce4U; |
@@ -508,6 +756,30 @@ static inline u32 fb_mmu_vpr_info_fetch_true_v(void) | |||
508 | { | 756 | { |
509 | return 0x00000001U; | 757 | return 0x00000001U; |
510 | } | 758 | } |
759 | static inline u32 fb_niso_cfg1_r(void) | ||
760 | { | ||
761 | return 0x00100c14U; | ||
762 | } | ||
763 | static inline u32 fb_niso_cfg1_sysmem_nvlink_f(u32 v) | ||
764 | { | ||
765 | return (v & 0x1U) << 17U; | ||
766 | } | ||
767 | static inline u32 fb_niso_cfg1_sysmem_nvlink_m(void) | ||
768 | { | ||
769 | return 0x1U << 17U; | ||
770 | } | ||
771 | static inline u32 fb_niso_cfg1_sysmem_nvlink_v(u32 r) | ||
772 | { | ||
773 | return (r >> 17U) & 0x1U; | ||
774 | } | ||
775 | static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_v(void) | ||
776 | { | ||
777 | return 0x00000001U; | ||
778 | } | ||
779 | static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_f(void) | ||
780 | { | ||
781 | return 0x20000U; | ||
782 | } | ||
511 | static inline u32 fb_niso_flush_sysmem_addr_r(void) | 783 | static inline u32 fb_niso_flush_sysmem_addr_r(void) |
512 | { | 784 | { |
513 | return 0x00100c10U; | 785 | return 0x00100c10U; |
@@ -1504,8 +1776,196 @@ static inline u32 fb_mmu_priv_level_mask_r(void) | |||
1504 | { | 1776 | { |
1505 | return 0x00100cdcU; | 1777 | return 0x00100cdcU; |
1506 | } | 1778 | } |
1779 | static inline u32 fb_mmu_priv_level_mask_write_violation_f(u32 v) | ||
1780 | { | ||
1781 | return (v & 0x1U) << 7U; | ||
1782 | } | ||
1507 | static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) | 1783 | static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) |
1508 | { | 1784 | { |
1509 | return 0x1U << 7U; | 1785 | return 0x1U << 7U; |
1510 | } | 1786 | } |
1787 | static inline u32 fb_mmu_priv_level_mask_write_violation_v(u32 r) | ||
1788 | { | ||
1789 | return (r >> 7U) & 0x1U; | ||
1790 | } | ||
1791 | static inline u32 fb_hshub_config0_r(void) | ||
1792 | { | ||
1793 | return 0x001fbc00U; | ||
1794 | } | ||
1795 | static inline u32 fb_hshub_config0_sysmem_nvlink_mask_f(u32 v) | ||
1796 | { | ||
1797 | return (v & 0xffffU) << 0U; | ||
1798 | } | ||
1799 | static inline u32 fb_hshub_config0_sysmem_nvlink_mask_m(void) | ||
1800 | { | ||
1801 | return 0xffffU << 0U; | ||
1802 | } | ||
1803 | static inline u32 fb_hshub_config0_sysmem_nvlink_mask_v(u32 r) | ||
1804 | { | ||
1805 | return (r >> 0U) & 0xffffU; | ||
1806 | } | ||
1807 | static inline u32 fb_hshub_config0_peer_pcie_mask_f(u32 v) | ||
1808 | { | ||
1809 | return (v & 0xffffU) << 16U; | ||
1810 | } | ||
1811 | static inline u32 fb_hshub_config0_peer_pcie_mask_v(u32 r) | ||
1812 | { | ||
1813 | return (r >> 16U) & 0xffffU; | ||
1814 | } | ||
1815 | static inline u32 fb_hshub_config1_r(void) | ||
1816 | { | ||
1817 | return 0x001fbc04U; | ||
1818 | } | ||
1819 | static inline u32 fb_hshub_config1_peer_0_nvlink_mask_f(u32 v) | ||
1820 | { | ||
1821 | return (v & 0xffU) << 0U; | ||
1822 | } | ||
1823 | static inline u32 fb_hshub_config1_peer_0_nvlink_mask_v(u32 r) | ||
1824 | { | ||
1825 | return (r >> 0U) & 0xffU; | ||
1826 | } | ||
1827 | static inline u32 fb_hshub_config1_peer_1_nvlink_mask_f(u32 v) | ||
1828 | { | ||
1829 | return (v & 0xffU) << 8U; | ||
1830 | } | ||
1831 | static inline u32 fb_hshub_config1_peer_1_nvlink_mask_v(u32 r) | ||
1832 | { | ||
1833 | return (r >> 8U) & 0xffU; | ||
1834 | } | ||
1835 | static inline u32 fb_hshub_config1_peer_2_nvlink_mask_f(u32 v) | ||
1836 | { | ||
1837 | return (v & 0xffU) << 16U; | ||
1838 | } | ||
1839 | static inline u32 fb_hshub_config1_peer_2_nvlink_mask_v(u32 r) | ||
1840 | { | ||
1841 | return (r >> 16U) & 0xffU; | ||
1842 | } | ||
1843 | static inline u32 fb_hshub_config1_peer_3_nvlink_mask_f(u32 v) | ||
1844 | { | ||
1845 | return (v & 0xffU) << 24U; | ||
1846 | } | ||
1847 | static inline u32 fb_hshub_config1_peer_3_nvlink_mask_v(u32 r) | ||
1848 | { | ||
1849 | return (r >> 24U) & 0xffU; | ||
1850 | } | ||
1851 | static inline u32 fb_hshub_config2_r(void) | ||
1852 | { | ||
1853 | return 0x001fbc08U; | ||
1854 | } | ||
1855 | static inline u32 fb_hshub_config2_peer_4_nvlink_mask_f(u32 v) | ||
1856 | { | ||
1857 | return (v & 0xffU) << 0U; | ||
1858 | } | ||
1859 | static inline u32 fb_hshub_config2_peer_4_nvlink_mask_v(u32 r) | ||
1860 | { | ||
1861 | return (r >> 0U) & 0xffU; | ||
1862 | } | ||
1863 | static inline u32 fb_hshub_config2_peer_5_nvlink_mask_f(u32 v) | ||
1864 | { | ||
1865 | return (v & 0xffU) << 8U; | ||
1866 | } | ||
1867 | static inline u32 fb_hshub_config2_peer_5_nvlink_mask_v(u32 r) | ||
1868 | { | ||
1869 | return (r >> 8U) & 0xffU; | ||
1870 | } | ||
1871 | static inline u32 fb_hshub_config2_peer_6_nvlink_mask_f(u32 v) | ||
1872 | { | ||
1873 | return (v & 0xffU) << 16U; | ||
1874 | } | ||
1875 | static inline u32 fb_hshub_config2_peer_6_nvlink_mask_v(u32 r) | ||
1876 | { | ||
1877 | return (r >> 16U) & 0xffU; | ||
1878 | } | ||
1879 | static inline u32 fb_hshub_config2_peer_7_nvlink_mask_f(u32 v) | ||
1880 | { | ||
1881 | return (v & 0xffU) << 24U; | ||
1882 | } | ||
1883 | static inline u32 fb_hshub_config2_peer_7_nvlink_mask_v(u32 r) | ||
1884 | { | ||
1885 | return (r >> 24U) & 0xffU; | ||
1886 | } | ||
1887 | static inline u32 fb_hshub_config6_r(void) | ||
1888 | { | ||
1889 | return 0x001fbc18U; | ||
1890 | } | ||
1891 | static inline u32 fb_hshub_config7_r(void) | ||
1892 | { | ||
1893 | return 0x001fbc1cU; | ||
1894 | } | ||
1895 | static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_f(u32 v) | ||
1896 | { | ||
1897 | return (v & 0xfU) << 0U; | ||
1898 | } | ||
1899 | static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_v(u32 r) | ||
1900 | { | ||
1901 | return (r >> 0U) & 0xfU; | ||
1902 | } | ||
1903 | static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_f(u32 v) | ||
1904 | { | ||
1905 | return (v & 0xfU) << 4U; | ||
1906 | } | ||
1907 | static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_v(u32 r) | ||
1908 | { | ||
1909 | return (r >> 4U) & 0xfU; | ||
1910 | } | ||
1911 | static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_f(u32 v) | ||
1912 | { | ||
1913 | return (v & 0xfU) << 8U; | ||
1914 | } | ||
1915 | static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_v(u32 r) | ||
1916 | { | ||
1917 | return (r >> 8U) & 0xfU; | ||
1918 | } | ||
1919 | static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_f(u32 v) | ||
1920 | { | ||
1921 | return (v & 0xfU) << 12U; | ||
1922 | } | ||
1923 | static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_v(u32 r) | ||
1924 | { | ||
1925 | return (r >> 12U) & 0xfU; | ||
1926 | } | ||
1927 | static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_f(u32 v) | ||
1928 | { | ||
1929 | return (v & 0xfU) << 16U; | ||
1930 | } | ||
1931 | static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_v(u32 r) | ||
1932 | { | ||
1933 | return (r >> 16U) & 0xfU; | ||
1934 | } | ||
1935 | static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_f(u32 v) | ||
1936 | { | ||
1937 | return (v & 0xfU) << 20U; | ||
1938 | } | ||
1939 | static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_v(u32 r) | ||
1940 | { | ||
1941 | return (r >> 20U) & 0xfU; | ||
1942 | } | ||
1943 | static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_f(u32 v) | ||
1944 | { | ||
1945 | return (v & 0xfU) << 24U; | ||
1946 | } | ||
1947 | static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_v(u32 r) | ||
1948 | { | ||
1949 | return (r >> 24U) & 0xfU; | ||
1950 | } | ||
1951 | static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_f(u32 v) | ||
1952 | { | ||
1953 | return (v & 0xfU) << 28U; | ||
1954 | } | ||
1955 | static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_v(u32 r) | ||
1956 | { | ||
1957 | return (r >> 28U) & 0xfU; | ||
1958 | } | ||
1959 | static inline u32 fb_hshub_nvl_cfg_priv_level_mask_r(void) | ||
1960 | { | ||
1961 | return 0x001fbc50U; | ||
1962 | } | ||
1963 | static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(u32 v) | ||
1964 | { | ||
1965 | return (v & 0x7U) << 4U; | ||
1966 | } | ||
1967 | static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(u32 r) | ||
1968 | { | ||
1969 | return (r >> 4U) & 0x7U; | ||
1970 | } | ||
1511 | #endif | 1971 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h index 2e28bdb8..8e475895 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | |||
@@ -184,6 +184,22 @@ static inline u32 gr_exception_sked_m(void) | |||
184 | { | 184 | { |
185 | return 0x1U << 8U; | 185 | return 0x1U << 8U; |
186 | } | 186 | } |
187 | static inline u32 gr_exception_pd_m(void) | ||
188 | { | ||
189 | return 0x1U << 2U; | ||
190 | } | ||
191 | static inline u32 gr_exception_scc_m(void) | ||
192 | { | ||
193 | return 0x1U << 3U; | ||
194 | } | ||
195 | static inline u32 gr_exception_ssync_m(void) | ||
196 | { | ||
197 | return 0x1U << 5U; | ||
198 | } | ||
199 | static inline u32 gr_exception_mme_m(void) | ||
200 | { | ||
201 | return 0x1U << 7U; | ||
202 | } | ||
187 | static inline u32 gr_exception1_r(void) | 203 | static inline u32 gr_exception1_r(void) |
188 | { | 204 | { |
189 | return 0x00400118U; | 205 | return 0x00400118U; |
@@ -232,6 +248,46 @@ static inline u32 gr_exception_en_ds_enabled_f(void) | |||
232 | { | 248 | { |
233 | return 0x10U; | 249 | return 0x10U; |
234 | } | 250 | } |
251 | static inline u32 gr_exception_en_pd_m(void) | ||
252 | { | ||
253 | return 0x1U << 2U; | ||
254 | } | ||
255 | static inline u32 gr_exception_en_pd_enabled_f(void) | ||
256 | { | ||
257 | return 0x4U; | ||
258 | } | ||
259 | static inline u32 gr_exception_en_scc_m(void) | ||
260 | { | ||
261 | return 0x1U << 3U; | ||
262 | } | ||
263 | static inline u32 gr_exception_en_scc_enabled_f(void) | ||
264 | { | ||
265 | return 0x8U; | ||
266 | } | ||
267 | static inline u32 gr_exception_en_ssync_m(void) | ||
268 | { | ||
269 | return 0x1U << 5U; | ||
270 | } | ||
271 | static inline u32 gr_exception_en_ssync_enabled_f(void) | ||
272 | { | ||
273 | return 0x20U; | ||
274 | } | ||
275 | static inline u32 gr_exception_en_mme_m(void) | ||
276 | { | ||
277 | return 0x1U << 7U; | ||
278 | } | ||
279 | static inline u32 gr_exception_en_mme_enabled_f(void) | ||
280 | { | ||
281 | return 0x80U; | ||
282 | } | ||
283 | static inline u32 gr_exception_en_sked_m(void) | ||
284 | { | ||
285 | return 0x1U << 8U; | ||
286 | } | ||
287 | static inline u32 gr_exception_en_sked_enabled_f(void) | ||
288 | { | ||
289 | return 0x100U; | ||
290 | } | ||
235 | static inline u32 gr_exception1_en_r(void) | 291 | static inline u32 gr_exception1_en_r(void) |
236 | { | 292 | { |
237 | return 0x00400130U; | 293 | return 0x00400130U; |
@@ -872,6 +928,10 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void) | |||
872 | { | 928 | { |
873 | return 0x80000000U; | 929 | return 0x80000000U; |
874 | } | 930 | } |
931 | static inline u32 gr_fe_hww_esr_info_r(void) | ||
932 | { | ||
933 | return 0x004041b0U; | ||
934 | } | ||
875 | static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) | 935 | static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) |
876 | { | 936 | { |
877 | return 0x00419eacU; | 937 | return 0x00419eacU; |
@@ -1000,6 +1060,10 @@ static inline u32 gr_mme_hww_esr_en_enable_f(void) | |||
1000 | { | 1060 | { |
1001 | return 0x80000000U; | 1061 | return 0x80000000U; |
1002 | } | 1062 | } |
1063 | static inline u32 gr_mme_hww_esr_info_r(void) | ||
1064 | { | ||
1065 | return 0x00404494U; | ||
1066 | } | ||
1003 | static inline u32 gr_memfmt_hww_esr_r(void) | 1067 | static inline u32 gr_memfmt_hww_esr_r(void) |
1004 | { | 1068 | { |
1005 | return 0x00404600U; | 1069 | return 0x00404600U; |
@@ -2372,6 +2436,18 @@ static inline u32 gr_scc_hww_esr_en_enable_f(void) | |||
2372 | { | 2436 | { |
2373 | return 0x80000000U; | 2437 | return 0x80000000U; |
2374 | } | 2438 | } |
2439 | static inline u32 gr_ssync_hww_esr_r(void) | ||
2440 | { | ||
2441 | return 0x00405a14U; | ||
2442 | } | ||
2443 | static inline u32 gr_ssync_hww_esr_reset_active_f(void) | ||
2444 | { | ||
2445 | return 0x40000000U; | ||
2446 | } | ||
2447 | static inline u32 gr_ssync_hww_esr_en_enable_f(void) | ||
2448 | { | ||
2449 | return 0x80000000U; | ||
2450 | } | ||
2375 | static inline u32 gr_sked_hww_esr_r(void) | 2451 | static inline u32 gr_sked_hww_esr_r(void) |
2376 | { | 2452 | { |
2377 | return 0x00407020U; | 2453 | return 0x00407020U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h new file mode 100644 index 00000000..c27e607c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h | |||
@@ -0,0 +1,331 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ioctrl_gv100_h_ | ||
57 | #define _hw_ioctrl_gv100_h_ | ||
58 | |||
59 | static inline u32 ioctrl_reset_r(void) | ||
60 | { | ||
61 | return 0x00000140U; | ||
62 | } | ||
63 | static inline u32 ioctrl_reset_sw_post_reset_delay_microseconds_v(void) | ||
64 | { | ||
65 | return 0x00000008U; | ||
66 | } | ||
67 | static inline u32 ioctrl_reset_linkreset_f(u32 v) | ||
68 | { | ||
69 | return (v & 0x3fU) << 8U; | ||
70 | } | ||
71 | static inline u32 ioctrl_reset_linkreset_m(void) | ||
72 | { | ||
73 | return 0x3fU << 8U; | ||
74 | } | ||
75 | static inline u32 ioctrl_reset_linkreset_v(u32 r) | ||
76 | { | ||
77 | return (r >> 8U) & 0x3fU; | ||
78 | } | ||
79 | static inline u32 ioctrl_debug_reset_r(void) | ||
80 | { | ||
81 | return 0x00000144U; | ||
82 | } | ||
83 | static inline u32 ioctrl_debug_reset_link_f(u32 v) | ||
84 | { | ||
85 | return (v & 0x3fU) << 0U; | ||
86 | } | ||
87 | static inline u32 ioctrl_debug_reset_link_m(void) | ||
88 | { | ||
89 | return 0x3fU << 0U; | ||
90 | } | ||
91 | static inline u32 ioctrl_debug_reset_link_v(u32 r) | ||
92 | { | ||
93 | return (r >> 0U) & 0x3fU; | ||
94 | } | ||
95 | static inline u32 ioctrl_debug_reset_common_f(u32 v) | ||
96 | { | ||
97 | return (v & 0x1U) << 31U; | ||
98 | } | ||
99 | static inline u32 ioctrl_debug_reset_common_m(void) | ||
100 | { | ||
101 | return 0x1U << 31U; | ||
102 | } | ||
103 | static inline u32 ioctrl_debug_reset_common_v(u32 r) | ||
104 | { | ||
105 | return (r >> 31U) & 0x1U; | ||
106 | } | ||
107 | static inline u32 ioctrl_clock_control_r(u32 i) | ||
108 | { | ||
109 | return 0x00000180U + i*4U; | ||
110 | } | ||
111 | static inline u32 ioctrl_clock_control__size_1_v(void) | ||
112 | { | ||
113 | return 0x00000006U; | ||
114 | } | ||
115 | static inline u32 ioctrl_clock_control_clkdis_f(u32 v) | ||
116 | { | ||
117 | return (v & 0x1U) << 0U; | ||
118 | } | ||
119 | static inline u32 ioctrl_clock_control_clkdis_m(void) | ||
120 | { | ||
121 | return 0x1U << 0U; | ||
122 | } | ||
123 | static inline u32 ioctrl_clock_control_clkdis_v(u32 r) | ||
124 | { | ||
125 | return (r >> 0U) & 0x1U; | ||
126 | } | ||
127 | static inline u32 ioctrl_top_intr_0_status_r(void) | ||
128 | { | ||
129 | return 0x00000200U; | ||
130 | } | ||
131 | static inline u32 ioctrl_top_intr_0_status_link_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x3fU) << 0U; | ||
134 | } | ||
135 | static inline u32 ioctrl_top_intr_0_status_link_m(void) | ||
136 | { | ||
137 | return 0x3fU << 0U; | ||
138 | } | ||
139 | static inline u32 ioctrl_top_intr_0_status_link_v(u32 r) | ||
140 | { | ||
141 | return (r >> 0U) & 0x3fU; | ||
142 | } | ||
143 | static inline u32 ioctrl_top_intr_0_status_common_f(u32 v) | ||
144 | { | ||
145 | return (v & 0x1U) << 31U; | ||
146 | } | ||
147 | static inline u32 ioctrl_top_intr_0_status_common_m(void) | ||
148 | { | ||
149 | return 0x1U << 31U; | ||
150 | } | ||
151 | static inline u32 ioctrl_top_intr_0_status_common_v(u32 r) | ||
152 | { | ||
153 | return (r >> 31U) & 0x1U; | ||
154 | } | ||
155 | static inline u32 ioctrl_common_intr_0_mask_r(void) | ||
156 | { | ||
157 | return 0x00000220U; | ||
158 | } | ||
159 | static inline u32 ioctrl_common_intr_0_mask_fatal_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x1U) << 0U; | ||
162 | } | ||
163 | static inline u32 ioctrl_common_intr_0_mask_fatal_v(u32 r) | ||
164 | { | ||
165 | return (r >> 0U) & 0x1U; | ||
166 | } | ||
167 | static inline u32 ioctrl_common_intr_0_mask_nonfatal_f(u32 v) | ||
168 | { | ||
169 | return (v & 0x1U) << 1U; | ||
170 | } | ||
171 | static inline u32 ioctrl_common_intr_0_mask_nonfatal_v(u32 r) | ||
172 | { | ||
173 | return (r >> 1U) & 0x1U; | ||
174 | } | ||
175 | static inline u32 ioctrl_common_intr_0_mask_correctable_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x1U) << 2U; | ||
178 | } | ||
179 | static inline u32 ioctrl_common_intr_0_mask_correctable_v(u32 r) | ||
180 | { | ||
181 | return (r >> 2U) & 0x1U; | ||
182 | } | ||
183 | static inline u32 ioctrl_common_intr_0_mask_intra_f(u32 v) | ||
184 | { | ||
185 | return (v & 0x1U) << 3U; | ||
186 | } | ||
187 | static inline u32 ioctrl_common_intr_0_mask_intra_v(u32 r) | ||
188 | { | ||
189 | return (r >> 3U) & 0x1U; | ||
190 | } | ||
191 | static inline u32 ioctrl_common_intr_0_mask_intrb_f(u32 v) | ||
192 | { | ||
193 | return (v & 0x1U) << 4U; | ||
194 | } | ||
195 | static inline u32 ioctrl_common_intr_0_mask_intrb_v(u32 r) | ||
196 | { | ||
197 | return (r >> 4U) & 0x1U; | ||
198 | } | ||
199 | static inline u32 ioctrl_common_intr_0_status_r(void) | ||
200 | { | ||
201 | return 0x00000224U; | ||
202 | } | ||
203 | static inline u32 ioctrl_common_intr_0_status_fatal_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x1U) << 0U; | ||
206 | } | ||
207 | static inline u32 ioctrl_common_intr_0_status_fatal_v(u32 r) | ||
208 | { | ||
209 | return (r >> 0U) & 0x1U; | ||
210 | } | ||
211 | static inline u32 ioctrl_common_intr_0_status_nonfatal_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x1U) << 1U; | ||
214 | } | ||
215 | static inline u32 ioctrl_common_intr_0_status_nonfatal_v(u32 r) | ||
216 | { | ||
217 | return (r >> 1U) & 0x1U; | ||
218 | } | ||
219 | static inline u32 ioctrl_common_intr_0_status_correctable_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x1U) << 2U; | ||
222 | } | ||
223 | static inline u32 ioctrl_common_intr_0_status_correctable_v(u32 r) | ||
224 | { | ||
225 | return (r >> 2U) & 0x1U; | ||
226 | } | ||
227 | static inline u32 ioctrl_common_intr_0_status_intra_f(u32 v) | ||
228 | { | ||
229 | return (v & 0x1U) << 3U; | ||
230 | } | ||
231 | static inline u32 ioctrl_common_intr_0_status_intra_v(u32 r) | ||
232 | { | ||
233 | return (r >> 3U) & 0x1U; | ||
234 | } | ||
235 | static inline u32 ioctrl_common_intr_0_status_intrb_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x1U) << 4U; | ||
238 | } | ||
239 | static inline u32 ioctrl_common_intr_0_status_intrb_v(u32 r) | ||
240 | { | ||
241 | return (r >> 4U) & 0x1U; | ||
242 | } | ||
243 | static inline u32 ioctrl_link_intr_0_mask_r(u32 i) | ||
244 | { | ||
245 | return 0x00000240U + i*20U; | ||
246 | } | ||
247 | static inline u32 ioctrl_link_intr_0_mask_fatal_f(u32 v) | ||
248 | { | ||
249 | return (v & 0x1U) << 0U; | ||
250 | } | ||
251 | static inline u32 ioctrl_link_intr_0_mask_fatal_v(u32 r) | ||
252 | { | ||
253 | return (r >> 0U) & 0x1U; | ||
254 | } | ||
255 | static inline u32 ioctrl_link_intr_0_mask_nonfatal_f(u32 v) | ||
256 | { | ||
257 | return (v & 0x1U) << 1U; | ||
258 | } | ||
259 | static inline u32 ioctrl_link_intr_0_mask_nonfatal_v(u32 r) | ||
260 | { | ||
261 | return (r >> 1U) & 0x1U; | ||
262 | } | ||
263 | static inline u32 ioctrl_link_intr_0_mask_correctable_f(u32 v) | ||
264 | { | ||
265 | return (v & 0x1U) << 2U; | ||
266 | } | ||
267 | static inline u32 ioctrl_link_intr_0_mask_correctable_v(u32 r) | ||
268 | { | ||
269 | return (r >> 2U) & 0x1U; | ||
270 | } | ||
271 | static inline u32 ioctrl_link_intr_0_mask_intra_f(u32 v) | ||
272 | { | ||
273 | return (v & 0x1U) << 3U; | ||
274 | } | ||
275 | static inline u32 ioctrl_link_intr_0_mask_intra_v(u32 r) | ||
276 | { | ||
277 | return (r >> 3U) & 0x1U; | ||
278 | } | ||
279 | static inline u32 ioctrl_link_intr_0_mask_intrb_f(u32 v) | ||
280 | { | ||
281 | return (v & 0x1U) << 4U; | ||
282 | } | ||
283 | static inline u32 ioctrl_link_intr_0_mask_intrb_v(u32 r) | ||
284 | { | ||
285 | return (r >> 4U) & 0x1U; | ||
286 | } | ||
287 | static inline u32 ioctrl_link_intr_0_status_r(u32 i) | ||
288 | { | ||
289 | return 0x00000244U + i*20U; | ||
290 | } | ||
291 | static inline u32 ioctrl_link_intr_0_status_fatal_f(u32 v) | ||
292 | { | ||
293 | return (v & 0x1U) << 0U; | ||
294 | } | ||
295 | static inline u32 ioctrl_link_intr_0_status_fatal_v(u32 r) | ||
296 | { | ||
297 | return (r >> 0U) & 0x1U; | ||
298 | } | ||
299 | static inline u32 ioctrl_link_intr_0_status_nonfatal_f(u32 v) | ||
300 | { | ||
301 | return (v & 0x1U) << 1U; | ||
302 | } | ||
303 | static inline u32 ioctrl_link_intr_0_status_nonfatal_v(u32 r) | ||
304 | { | ||
305 | return (r >> 1U) & 0x1U; | ||
306 | } | ||
307 | static inline u32 ioctrl_link_intr_0_status_correctable_f(u32 v) | ||
308 | { | ||
309 | return (v & 0x1U) << 2U; | ||
310 | } | ||
311 | static inline u32 ioctrl_link_intr_0_status_correctable_v(u32 r) | ||
312 | { | ||
313 | return (r >> 2U) & 0x1U; | ||
314 | } | ||
315 | static inline u32 ioctrl_link_intr_0_status_intra_f(u32 v) | ||
316 | { | ||
317 | return (v & 0x1U) << 3U; | ||
318 | } | ||
319 | static inline u32 ioctrl_link_intr_0_status_intra_v(u32 r) | ||
320 | { | ||
321 | return (r >> 3U) & 0x1U; | ||
322 | } | ||
323 | static inline u32 ioctrl_link_intr_0_status_intrb_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x1U) << 4U; | ||
326 | } | ||
327 | static inline u32 ioctrl_link_intr_0_status_intrb_v(u32 r) | ||
328 | { | ||
329 | return (r >> 4U) & 0x1U; | ||
330 | } | ||
331 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h new file mode 100644 index 00000000..5747a9ba --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h | |||
@@ -0,0 +1,331 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ioctrlmif_gv100_h_ | ||
57 | #define _hw_ioctrlmif_gv100_h_ | ||
58 | |||
59 | static inline u32 ioctrlmif_rx_err_contain_en_0_r(void) | ||
60 | { | ||
61 | return 0x00000e0cU; | ||
62 | } | ||
63 | static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(u32 v) | ||
64 | { | ||
65 | return (v & 0x1U) << 3U; | ||
66 | } | ||
67 | static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m(void) | ||
68 | { | ||
69 | return 0x1U << 3U; | ||
70 | } | ||
71 | static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(u32 r) | ||
72 | { | ||
73 | return (r >> 3U) & 0x1U; | ||
74 | } | ||
75 | static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_v(void) | ||
76 | { | ||
77 | return 0x00000001U; | ||
78 | } | ||
79 | static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_f(void) | ||
80 | { | ||
81 | return 0x8U; | ||
82 | } | ||
83 | static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(u32 v) | ||
84 | { | ||
85 | return (v & 0x1U) << 4U; | ||
86 | } | ||
87 | static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m(void) | ||
88 | { | ||
89 | return 0x1U << 4U; | ||
90 | } | ||
91 | static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(u32 r) | ||
92 | { | ||
93 | return (r >> 4U) & 0x1U; | ||
94 | } | ||
95 | static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v(void) | ||
96 | { | ||
97 | return 0x00000001U; | ||
98 | } | ||
99 | static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f(void) | ||
100 | { | ||
101 | return 0x10U; | ||
102 | } | ||
103 | static inline u32 ioctrlmif_rx_err_log_en_0_r(void) | ||
104 | { | ||
105 | return 0x00000e04U; | ||
106 | } | ||
107 | static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(u32 v) | ||
108 | { | ||
109 | return (v & 0x1U) << 3U; | ||
110 | } | ||
111 | static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m(void) | ||
112 | { | ||
113 | return 0x1U << 3U; | ||
114 | } | ||
115 | static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(u32 r) | ||
116 | { | ||
117 | return (r >> 3U) & 0x1U; | ||
118 | } | ||
119 | static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(u32 v) | ||
120 | { | ||
121 | return (v & 0x1U) << 4U; | ||
122 | } | ||
123 | static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m(void) | ||
124 | { | ||
125 | return 0x1U << 4U; | ||
126 | } | ||
127 | static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(u32 r) | ||
128 | { | ||
129 | return (r >> 4U) & 0x1U; | ||
130 | } | ||
131 | static inline u32 ioctrlmif_rx_err_report_en_0_r(void) | ||
132 | { | ||
133 | return 0x00000e08U; | ||
134 | } | ||
135 | static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(u32 v) | ||
136 | { | ||
137 | return (v & 0x1U) << 3U; | ||
138 | } | ||
139 | static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m(void) | ||
140 | { | ||
141 | return 0x1U << 3U; | ||
142 | } | ||
143 | static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(u32 r) | ||
144 | { | ||
145 | return (r >> 3U) & 0x1U; | ||
146 | } | ||
147 | static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(u32 v) | ||
148 | { | ||
149 | return (v & 0x1U) << 4U; | ||
150 | } | ||
151 | static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m(void) | ||
152 | { | ||
153 | return 0x1U << 4U; | ||
154 | } | ||
155 | static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(u32 r) | ||
156 | { | ||
157 | return (r >> 4U) & 0x1U; | ||
158 | } | ||
159 | static inline u32 ioctrlmif_rx_err_status_0_r(void) | ||
160 | { | ||
161 | return 0x00000e00U; | ||
162 | } | ||
163 | static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_f(u32 v) | ||
164 | { | ||
165 | return (v & 0x1U) << 3U; | ||
166 | } | ||
167 | static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_m(void) | ||
168 | { | ||
169 | return 0x1U << 3U; | ||
170 | } | ||
171 | static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_v(u32 r) | ||
172 | { | ||
173 | return (r >> 3U) & 0x1U; | ||
174 | } | ||
175 | static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x1U) << 4U; | ||
178 | } | ||
179 | static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_m(void) | ||
180 | { | ||
181 | return 0x1U << 4U; | ||
182 | } | ||
183 | static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(u32 r) | ||
184 | { | ||
185 | return (r >> 4U) & 0x1U; | ||
186 | } | ||
187 | static inline u32 ioctrlmif_rx_err_first_0_r(void) | ||
188 | { | ||
189 | return 0x00000e14U; | ||
190 | } | ||
191 | static inline u32 ioctrlmif_tx_err_contain_en_0_r(void) | ||
192 | { | ||
193 | return 0x00000a90U; | ||
194 | } | ||
195 | static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x1U) << 0U; | ||
198 | } | ||
199 | static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m(void) | ||
200 | { | ||
201 | return 0x1U << 0U; | ||
202 | } | ||
203 | static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(u32 r) | ||
204 | { | ||
205 | return (r >> 0U) & 0x1U; | ||
206 | } | ||
207 | static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v(void) | ||
208 | { | ||
209 | return 0x00000001U; | ||
210 | } | ||
211 | static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f(void) | ||
212 | { | ||
213 | return 0x1U; | ||
214 | } | ||
215 | static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(u32 v) | ||
216 | { | ||
217 | return (v & 0x1U) << 1U; | ||
218 | } | ||
219 | static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m(void) | ||
220 | { | ||
221 | return 0x1U << 1U; | ||
222 | } | ||
223 | static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(u32 r) | ||
224 | { | ||
225 | return (r >> 1U) & 0x1U; | ||
226 | } | ||
227 | static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v(void) | ||
228 | { | ||
229 | return 0x00000001U; | ||
230 | } | ||
231 | static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f(void) | ||
232 | { | ||
233 | return 0x2U; | ||
234 | } | ||
235 | static inline u32 ioctrlmif_tx_err_log_en_0_r(void) | ||
236 | { | ||
237 | return 0x00000a88U; | ||
238 | } | ||
239 | static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x1U) << 0U; | ||
242 | } | ||
243 | static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_m(void) | ||
244 | { | ||
245 | return 0x1U << 0U; | ||
246 | } | ||
247 | static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(u32 r) | ||
248 | { | ||
249 | return (r >> 0U) & 0x1U; | ||
250 | } | ||
251 | static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(u32 v) | ||
252 | { | ||
253 | return (v & 0x1U) << 1U; | ||
254 | } | ||
255 | static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m(void) | ||
256 | { | ||
257 | return 0x1U << 1U; | ||
258 | } | ||
259 | static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(u32 r) | ||
260 | { | ||
261 | return (r >> 1U) & 0x1U; | ||
262 | } | ||
263 | static inline u32 ioctrlmif_tx_err_report_en_0_r(void) | ||
264 | { | ||
265 | return 0x00000e08U; | ||
266 | } | ||
267 | static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(u32 v) | ||
268 | { | ||
269 | return (v & 0x1U) << 0U; | ||
270 | } | ||
271 | static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_m(void) | ||
272 | { | ||
273 | return 0x1U << 0U; | ||
274 | } | ||
275 | static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(u32 r) | ||
276 | { | ||
277 | return (r >> 0U) & 0x1U; | ||
278 | } | ||
279 | static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(u32 v) | ||
280 | { | ||
281 | return (v & 0x1U) << 1U; | ||
282 | } | ||
283 | static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m(void) | ||
284 | { | ||
285 | return 0x1U << 1U; | ||
286 | } | ||
287 | static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(u32 r) | ||
288 | { | ||
289 | return (r >> 1U) & 0x1U; | ||
290 | } | ||
291 | static inline u32 ioctrlmif_tx_err_status_0_r(void) | ||
292 | { | ||
293 | return 0x00000a84U; | ||
294 | } | ||
295 | static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x1U) << 0U; | ||
298 | } | ||
299 | static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_m(void) | ||
300 | { | ||
301 | return 0x1U << 0U; | ||
302 | } | ||
303 | static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_v(u32 r) | ||
304 | { | ||
305 | return (r >> 0U) & 0x1U; | ||
306 | } | ||
307 | static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_f(u32 v) | ||
308 | { | ||
309 | return (v & 0x1U) << 1U; | ||
310 | } | ||
311 | static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_m(void) | ||
312 | { | ||
313 | return 0x1U << 1U; | ||
314 | } | ||
315 | static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_v(u32 r) | ||
316 | { | ||
317 | return (r >> 1U) & 0x1U; | ||
318 | } | ||
319 | static inline u32 ioctrlmif_tx_err_first_0_r(void) | ||
320 | { | ||
321 | return 0x00000a98U; | ||
322 | } | ||
323 | static inline u32 ioctrlmif_tx_ctrl_buffer_ready_r(void) | ||
324 | { | ||
325 | return 0x00000a7cU; | ||
326 | } | ||
327 | static inline u32 ioctrlmif_rx_ctrl_buffer_ready_r(void) | ||
328 | { | ||
329 | return 0x00000dfcU; | ||
330 | } | ||
331 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h index f367991e..fb558d2f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -108,6 +108,10 @@ static inline u32 mc_intr_pbus_pending_f(void) | |||
108 | { | 108 | { |
109 | return 0x10000000U; | 109 | return 0x10000000U; |
110 | } | 110 | } |
111 | static inline u32 mc_intr_nvlink_pending_f(void) | ||
112 | { | ||
113 | return 0x400000U; | ||
114 | } | ||
111 | static inline u32 mc_intr_en_r(u32 i) | 115 | static inline u32 mc_intr_en_r(u32 i) |
112 | { | 116 | { |
113 | return 0x00000140U + i*4U; | 117 | return 0x00000140U + i*4U; |
@@ -204,6 +208,22 @@ static inline u32 mc_enable_nvdec_enabled_f(void) | |||
204 | { | 208 | { |
205 | return 0x8000U; | 209 | return 0x8000U; |
206 | } | 210 | } |
211 | static inline u32 mc_enable_nvlink_disabled_v(void) | ||
212 | { | ||
213 | return 0x00000000U; | ||
214 | } | ||
215 | static inline u32 mc_enable_nvlink_disabled_f(void) | ||
216 | { | ||
217 | return 0x0U; | ||
218 | } | ||
219 | static inline u32 mc_enable_nvlink_enabled_v(void) | ||
220 | { | ||
221 | return 0x00000001U; | ||
222 | } | ||
223 | static inline u32 mc_enable_nvlink_enabled_f(void) | ||
224 | { | ||
225 | return 0x2000000U; | ||
226 | } | ||
207 | static inline u32 mc_intr_ltc_r(void) | 227 | static inline u32 mc_intr_ltc_r(void) |
208 | { | 228 | { |
209 | return 0x000001c0U; | 229 | return 0x000001c0U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h new file mode 100644 index 00000000..c59a6e6b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h | |||
@@ -0,0 +1,919 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_minion_gv100_h_ | ||
57 | #define _hw_minion_gv100_h_ | ||
58 | |||
59 | static inline u32 minion_minion_status_r(void) | ||
60 | { | ||
61 | return 0x00000830U; | ||
62 | } | ||
63 | static inline u32 minion_minion_status_status_f(u32 v) | ||
64 | { | ||
65 | return (v & 0xffU) << 0U; | ||
66 | } | ||
67 | static inline u32 minion_minion_status_status_m(void) | ||
68 | { | ||
69 | return 0xffU << 0U; | ||
70 | } | ||
71 | static inline u32 minion_minion_status_status_v(u32 r) | ||
72 | { | ||
73 | return (r >> 0U) & 0xffU; | ||
74 | } | ||
75 | static inline u32 minion_minion_status_status_boot_v(void) | ||
76 | { | ||
77 | return 0x00000001U; | ||
78 | } | ||
79 | static inline u32 minion_minion_status_status_boot_f(void) | ||
80 | { | ||
81 | return 0x1U; | ||
82 | } | ||
83 | static inline u32 minion_minion_status_intr_code_f(u32 v) | ||
84 | { | ||
85 | return (v & 0xffffffU) << 8U; | ||
86 | } | ||
87 | static inline u32 minion_minion_status_intr_code_m(void) | ||
88 | { | ||
89 | return 0xffffffU << 8U; | ||
90 | } | ||
91 | static inline u32 minion_minion_status_intr_code_v(u32 r) | ||
92 | { | ||
93 | return (r >> 8U) & 0xffffffU; | ||
94 | } | ||
95 | static inline u32 minion_falcon_irqstat_r(void) | ||
96 | { | ||
97 | return 0x00000008U; | ||
98 | } | ||
99 | static inline u32 minion_falcon_irqstat_halt_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1U) << 4U; | ||
102 | } | ||
103 | static inline u32 minion_falcon_irqstat_halt_v(u32 r) | ||
104 | { | ||
105 | return (r >> 4U) & 0x1U; | ||
106 | } | ||
107 | static inline u32 minion_falcon_irqmask_r(void) | ||
108 | { | ||
109 | return 0x00000018U; | ||
110 | } | ||
111 | static inline u32 minion_falcon_irqsclr_r(void) | ||
112 | { | ||
113 | return 0x00000004U; | ||
114 | } | ||
115 | static inline u32 minion_falcon_irqsset_r(void) | ||
116 | { | ||
117 | return 0x00000000U; | ||
118 | } | ||
119 | static inline u32 minion_falcon_irqmset_r(void) | ||
120 | { | ||
121 | return 0x00000010U; | ||
122 | } | ||
123 | static inline u32 minion_falcon_irqmset_wdtmr_f(u32 v) | ||
124 | { | ||
125 | return (v & 0x1U) << 1U; | ||
126 | } | ||
127 | static inline u32 minion_falcon_irqmset_wdtmr_m(void) | ||
128 | { | ||
129 | return 0x1U << 1U; | ||
130 | } | ||
131 | static inline u32 minion_falcon_irqmset_wdtmr_v(u32 r) | ||
132 | { | ||
133 | return (r >> 1U) & 0x1U; | ||
134 | } | ||
135 | static inline u32 minion_falcon_irqmset_wdtmr_set_v(void) | ||
136 | { | ||
137 | return 0x00000001U; | ||
138 | } | ||
139 | static inline u32 minion_falcon_irqmset_wdtmr_set_f(void) | ||
140 | { | ||
141 | return 0x2U; | ||
142 | } | ||
143 | static inline u32 minion_falcon_irqmset_halt_f(u32 v) | ||
144 | { | ||
145 | return (v & 0x1U) << 4U; | ||
146 | } | ||
147 | static inline u32 minion_falcon_irqmset_halt_m(void) | ||
148 | { | ||
149 | return 0x1U << 4U; | ||
150 | } | ||
151 | static inline u32 minion_falcon_irqmset_halt_v(u32 r) | ||
152 | { | ||
153 | return (r >> 4U) & 0x1U; | ||
154 | } | ||
155 | static inline u32 minion_falcon_irqmset_halt_set_v(void) | ||
156 | { | ||
157 | return 0x00000001U; | ||
158 | } | ||
159 | static inline u32 minion_falcon_irqmset_halt_set_f(void) | ||
160 | { | ||
161 | return 0x10U; | ||
162 | } | ||
163 | static inline u32 minion_falcon_irqmset_exterr_f(u32 v) | ||
164 | { | ||
165 | return (v & 0x1U) << 5U; | ||
166 | } | ||
167 | static inline u32 minion_falcon_irqmset_exterr_m(void) | ||
168 | { | ||
169 | return 0x1U << 5U; | ||
170 | } | ||
171 | static inline u32 minion_falcon_irqmset_exterr_v(u32 r) | ||
172 | { | ||
173 | return (r >> 5U) & 0x1U; | ||
174 | } | ||
175 | static inline u32 minion_falcon_irqmset_exterr_set_v(void) | ||
176 | { | ||
177 | return 0x00000001U; | ||
178 | } | ||
179 | static inline u32 minion_falcon_irqmset_exterr_set_f(void) | ||
180 | { | ||
181 | return 0x20U; | ||
182 | } | ||
183 | static inline u32 minion_falcon_irqmset_swgen0_f(u32 v) | ||
184 | { | ||
185 | return (v & 0x1U) << 6U; | ||
186 | } | ||
187 | static inline u32 minion_falcon_irqmset_swgen0_m(void) | ||
188 | { | ||
189 | return 0x1U << 6U; | ||
190 | } | ||
191 | static inline u32 minion_falcon_irqmset_swgen0_v(u32 r) | ||
192 | { | ||
193 | return (r >> 6U) & 0x1U; | ||
194 | } | ||
195 | static inline u32 minion_falcon_irqmset_swgen0_set_v(void) | ||
196 | { | ||
197 | return 0x00000001U; | ||
198 | } | ||
199 | static inline u32 minion_falcon_irqmset_swgen0_set_f(void) | ||
200 | { | ||
201 | return 0x40U; | ||
202 | } | ||
203 | static inline u32 minion_falcon_irqmset_swgen1_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x1U) << 7U; | ||
206 | } | ||
207 | static inline u32 minion_falcon_irqmset_swgen1_m(void) | ||
208 | { | ||
209 | return 0x1U << 7U; | ||
210 | } | ||
211 | static inline u32 minion_falcon_irqmset_swgen1_v(u32 r) | ||
212 | { | ||
213 | return (r >> 7U) & 0x1U; | ||
214 | } | ||
215 | static inline u32 minion_falcon_irqmset_swgen1_set_v(void) | ||
216 | { | ||
217 | return 0x00000001U; | ||
218 | } | ||
219 | static inline u32 minion_falcon_irqmset_swgen1_set_f(void) | ||
220 | { | ||
221 | return 0x80U; | ||
222 | } | ||
223 | static inline u32 minion_falcon_irqdest_r(void) | ||
224 | { | ||
225 | return 0x0000001cU; | ||
226 | } | ||
227 | static inline u32 minion_falcon_irqdest_host_wdtmr_f(u32 v) | ||
228 | { | ||
229 | return (v & 0x1U) << 1U; | ||
230 | } | ||
231 | static inline u32 minion_falcon_irqdest_host_wdtmr_m(void) | ||
232 | { | ||
233 | return 0x1U << 1U; | ||
234 | } | ||
235 | static inline u32 minion_falcon_irqdest_host_wdtmr_v(u32 r) | ||
236 | { | ||
237 | return (r >> 1U) & 0x1U; | ||
238 | } | ||
239 | static inline u32 minion_falcon_irqdest_host_wdtmr_host_v(void) | ||
240 | { | ||
241 | return 0x00000001U; | ||
242 | } | ||
243 | static inline u32 minion_falcon_irqdest_host_wdtmr_host_f(void) | ||
244 | { | ||
245 | return 0x2U; | ||
246 | } | ||
247 | static inline u32 minion_falcon_irqdest_host_halt_f(u32 v) | ||
248 | { | ||
249 | return (v & 0x1U) << 4U; | ||
250 | } | ||
251 | static inline u32 minion_falcon_irqdest_host_halt_m(void) | ||
252 | { | ||
253 | return 0x1U << 4U; | ||
254 | } | ||
255 | static inline u32 minion_falcon_irqdest_host_halt_v(u32 r) | ||
256 | { | ||
257 | return (r >> 4U) & 0x1U; | ||
258 | } | ||
259 | static inline u32 minion_falcon_irqdest_host_halt_host_v(void) | ||
260 | { | ||
261 | return 0x00000001U; | ||
262 | } | ||
263 | static inline u32 minion_falcon_irqdest_host_halt_host_f(void) | ||
264 | { | ||
265 | return 0x10U; | ||
266 | } | ||
267 | static inline u32 minion_falcon_irqdest_host_exterr_f(u32 v) | ||
268 | { | ||
269 | return (v & 0x1U) << 5U; | ||
270 | } | ||
271 | static inline u32 minion_falcon_irqdest_host_exterr_m(void) | ||
272 | { | ||
273 | return 0x1U << 5U; | ||
274 | } | ||
275 | static inline u32 minion_falcon_irqdest_host_exterr_v(u32 r) | ||
276 | { | ||
277 | return (r >> 5U) & 0x1U; | ||
278 | } | ||
279 | static inline u32 minion_falcon_irqdest_host_exterr_host_v(void) | ||
280 | { | ||
281 | return 0x00000001U; | ||
282 | } | ||
283 | static inline u32 minion_falcon_irqdest_host_exterr_host_f(void) | ||
284 | { | ||
285 | return 0x20U; | ||
286 | } | ||
287 | static inline u32 minion_falcon_irqdest_host_swgen0_f(u32 v) | ||
288 | { | ||
289 | return (v & 0x1U) << 6U; | ||
290 | } | ||
291 | static inline u32 minion_falcon_irqdest_host_swgen0_m(void) | ||
292 | { | ||
293 | return 0x1U << 6U; | ||
294 | } | ||
295 | static inline u32 minion_falcon_irqdest_host_swgen0_v(u32 r) | ||
296 | { | ||
297 | return (r >> 6U) & 0x1U; | ||
298 | } | ||
299 | static inline u32 minion_falcon_irqdest_host_swgen0_host_v(void) | ||
300 | { | ||
301 | return 0x00000001U; | ||
302 | } | ||
303 | static inline u32 minion_falcon_irqdest_host_swgen0_host_f(void) | ||
304 | { | ||
305 | return 0x40U; | ||
306 | } | ||
307 | static inline u32 minion_falcon_irqdest_host_swgen1_f(u32 v) | ||
308 | { | ||
309 | return (v & 0x1U) << 7U; | ||
310 | } | ||
311 | static inline u32 minion_falcon_irqdest_host_swgen1_m(void) | ||
312 | { | ||
313 | return 0x1U << 7U; | ||
314 | } | ||
315 | static inline u32 minion_falcon_irqdest_host_swgen1_v(u32 r) | ||
316 | { | ||
317 | return (r >> 7U) & 0x1U; | ||
318 | } | ||
319 | static inline u32 minion_falcon_irqdest_host_swgen1_host_v(void) | ||
320 | { | ||
321 | return 0x00000001U; | ||
322 | } | ||
323 | static inline u32 minion_falcon_irqdest_host_swgen1_host_f(void) | ||
324 | { | ||
325 | return 0x80U; | ||
326 | } | ||
327 | static inline u32 minion_falcon_irqdest_target_wdtmr_f(u32 v) | ||
328 | { | ||
329 | return (v & 0x1U) << 17U; | ||
330 | } | ||
331 | static inline u32 minion_falcon_irqdest_target_wdtmr_m(void) | ||
332 | { | ||
333 | return 0x1U << 17U; | ||
334 | } | ||
335 | static inline u32 minion_falcon_irqdest_target_wdtmr_v(u32 r) | ||
336 | { | ||
337 | return (r >> 17U) & 0x1U; | ||
338 | } | ||
339 | static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_v(void) | ||
340 | { | ||
341 | return 0x00000000U; | ||
342 | } | ||
343 | static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_f(void) | ||
344 | { | ||
345 | return 0x0U; | ||
346 | } | ||
347 | static inline u32 minion_falcon_irqdest_target_halt_f(u32 v) | ||
348 | { | ||
349 | return (v & 0x1U) << 20U; | ||
350 | } | ||
351 | static inline u32 minion_falcon_irqdest_target_halt_m(void) | ||
352 | { | ||
353 | return 0x1U << 20U; | ||
354 | } | ||
355 | static inline u32 minion_falcon_irqdest_target_halt_v(u32 r) | ||
356 | { | ||
357 | return (r >> 20U) & 0x1U; | ||
358 | } | ||
359 | static inline u32 minion_falcon_irqdest_target_halt_host_normal_v(void) | ||
360 | { | ||
361 | return 0x00000000U; | ||
362 | } | ||
363 | static inline u32 minion_falcon_irqdest_target_halt_host_normal_f(void) | ||
364 | { | ||
365 | return 0x0U; | ||
366 | } | ||
367 | static inline u32 minion_falcon_irqdest_target_exterr_f(u32 v) | ||
368 | { | ||
369 | return (v & 0x1U) << 21U; | ||
370 | } | ||
371 | static inline u32 minion_falcon_irqdest_target_exterr_m(void) | ||
372 | { | ||
373 | return 0x1U << 21U; | ||
374 | } | ||
375 | static inline u32 minion_falcon_irqdest_target_exterr_v(u32 r) | ||
376 | { | ||
377 | return (r >> 21U) & 0x1U; | ||
378 | } | ||
379 | static inline u32 minion_falcon_irqdest_target_exterr_host_normal_v(void) | ||
380 | { | ||
381 | return 0x00000000U; | ||
382 | } | ||
383 | static inline u32 minion_falcon_irqdest_target_exterr_host_normal_f(void) | ||
384 | { | ||
385 | return 0x0U; | ||
386 | } | ||
387 | static inline u32 minion_falcon_irqdest_target_swgen0_f(u32 v) | ||
388 | { | ||
389 | return (v & 0x1U) << 22U; | ||
390 | } | ||
391 | static inline u32 minion_falcon_irqdest_target_swgen0_m(void) | ||
392 | { | ||
393 | return 0x1U << 22U; | ||
394 | } | ||
395 | static inline u32 minion_falcon_irqdest_target_swgen0_v(u32 r) | ||
396 | { | ||
397 | return (r >> 22U) & 0x1U; | ||
398 | } | ||
399 | static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_v(void) | ||
400 | { | ||
401 | return 0x00000000U; | ||
402 | } | ||
403 | static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_f(void) | ||
404 | { | ||
405 | return 0x0U; | ||
406 | } | ||
407 | static inline u32 minion_falcon_irqdest_target_swgen1_f(u32 v) | ||
408 | { | ||
409 | return (v & 0x1U) << 23U; | ||
410 | } | ||
411 | static inline u32 minion_falcon_irqdest_target_swgen1_m(void) | ||
412 | { | ||
413 | return 0x1U << 23U; | ||
414 | } | ||
415 | static inline u32 minion_falcon_irqdest_target_swgen1_v(u32 r) | ||
416 | { | ||
417 | return (r >> 23U) & 0x1U; | ||
418 | } | ||
419 | static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_v(void) | ||
420 | { | ||
421 | return 0x00000000U; | ||
422 | } | ||
423 | static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_f(void) | ||
424 | { | ||
425 | return 0x0U; | ||
426 | } | ||
427 | static inline u32 minion_falcon_os_r(void) | ||
428 | { | ||
429 | return 0x00000080U; | ||
430 | } | ||
431 | static inline u32 minion_falcon_mailbox1_r(void) | ||
432 | { | ||
433 | return 0x00000044U; | ||
434 | } | ||
435 | static inline u32 minion_minion_intr_r(void) | ||
436 | { | ||
437 | return 0x00000810U; | ||
438 | } | ||
439 | static inline u32 minion_minion_intr_fatal_f(u32 v) | ||
440 | { | ||
441 | return (v & 0x1U) << 0U; | ||
442 | } | ||
443 | static inline u32 minion_minion_intr_fatal_m(void) | ||
444 | { | ||
445 | return 0x1U << 0U; | ||
446 | } | ||
447 | static inline u32 minion_minion_intr_fatal_v(u32 r) | ||
448 | { | ||
449 | return (r >> 0U) & 0x1U; | ||
450 | } | ||
451 | static inline u32 minion_minion_intr_nonfatal_f(u32 v) | ||
452 | { | ||
453 | return (v & 0x1U) << 1U; | ||
454 | } | ||
455 | static inline u32 minion_minion_intr_nonfatal_m(void) | ||
456 | { | ||
457 | return 0x1U << 1U; | ||
458 | } | ||
459 | static inline u32 minion_minion_intr_nonfatal_v(u32 r) | ||
460 | { | ||
461 | return (r >> 1U) & 0x1U; | ||
462 | } | ||
463 | static inline u32 minion_minion_intr_falcon_stall_f(u32 v) | ||
464 | { | ||
465 | return (v & 0x1U) << 2U; | ||
466 | } | ||
467 | static inline u32 minion_minion_intr_falcon_stall_m(void) | ||
468 | { | ||
469 | return 0x1U << 2U; | ||
470 | } | ||
471 | static inline u32 minion_minion_intr_falcon_stall_v(u32 r) | ||
472 | { | ||
473 | return (r >> 2U) & 0x1U; | ||
474 | } | ||
475 | static inline u32 minion_minion_intr_falcon_nostall_f(u32 v) | ||
476 | { | ||
477 | return (v & 0x1U) << 3U; | ||
478 | } | ||
479 | static inline u32 minion_minion_intr_falcon_nostall_m(void) | ||
480 | { | ||
481 | return 0x1U << 3U; | ||
482 | } | ||
483 | static inline u32 minion_minion_intr_falcon_nostall_v(u32 r) | ||
484 | { | ||
485 | return (r >> 3U) & 0x1U; | ||
486 | } | ||
487 | static inline u32 minion_minion_intr_link_f(u32 v) | ||
488 | { | ||
489 | return (v & 0xffffU) << 16U; | ||
490 | } | ||
491 | static inline u32 minion_minion_intr_link_m(void) | ||
492 | { | ||
493 | return 0xffffU << 16U; | ||
494 | } | ||
495 | static inline u32 minion_minion_intr_link_v(u32 r) | ||
496 | { | ||
497 | return (r >> 16U) & 0xffffU; | ||
498 | } | ||
499 | static inline u32 minion_minion_intr_nonstall_en_r(void) | ||
500 | { | ||
501 | return 0x0000081cU; | ||
502 | } | ||
503 | static inline u32 minion_minion_intr_stall_en_r(void) | ||
504 | { | ||
505 | return 0x00000818U; | ||
506 | } | ||
507 | static inline u32 minion_minion_intr_stall_en_fatal_f(u32 v) | ||
508 | { | ||
509 | return (v & 0x1U) << 0U; | ||
510 | } | ||
511 | static inline u32 minion_minion_intr_stall_en_fatal_m(void) | ||
512 | { | ||
513 | return 0x1U << 0U; | ||
514 | } | ||
515 | static inline u32 minion_minion_intr_stall_en_fatal_v(u32 r) | ||
516 | { | ||
517 | return (r >> 0U) & 0x1U; | ||
518 | } | ||
519 | static inline u32 minion_minion_intr_stall_en_fatal_enable_v(void) | ||
520 | { | ||
521 | return 0x00000001U; | ||
522 | } | ||
523 | static inline u32 minion_minion_intr_stall_en_fatal_enable_f(void) | ||
524 | { | ||
525 | return 0x1U; | ||
526 | } | ||
527 | static inline u32 minion_minion_intr_stall_en_fatal_disable_v(void) | ||
528 | { | ||
529 | return 0x00000000U; | ||
530 | } | ||
531 | static inline u32 minion_minion_intr_stall_en_fatal_disable_f(void) | ||
532 | { | ||
533 | return 0x0U; | ||
534 | } | ||
535 | static inline u32 minion_minion_intr_stall_en_nonfatal_f(u32 v) | ||
536 | { | ||
537 | return (v & 0x1U) << 1U; | ||
538 | } | ||
539 | static inline u32 minion_minion_intr_stall_en_nonfatal_m(void) | ||
540 | { | ||
541 | return 0x1U << 1U; | ||
542 | } | ||
543 | static inline u32 minion_minion_intr_stall_en_nonfatal_v(u32 r) | ||
544 | { | ||
545 | return (r >> 1U) & 0x1U; | ||
546 | } | ||
547 | static inline u32 minion_minion_intr_stall_en_nonfatal_enable_v(void) | ||
548 | { | ||
549 | return 0x00000001U; | ||
550 | } | ||
551 | static inline u32 minion_minion_intr_stall_en_nonfatal_enable_f(void) | ||
552 | { | ||
553 | return 0x2U; | ||
554 | } | ||
555 | static inline u32 minion_minion_intr_stall_en_nonfatal_disable_v(void) | ||
556 | { | ||
557 | return 0x00000000U; | ||
558 | } | ||
559 | static inline u32 minion_minion_intr_stall_en_nonfatal_disable_f(void) | ||
560 | { | ||
561 | return 0x0U; | ||
562 | } | ||
563 | static inline u32 minion_minion_intr_stall_en_falcon_stall_f(u32 v) | ||
564 | { | ||
565 | return (v & 0x1U) << 2U; | ||
566 | } | ||
567 | static inline u32 minion_minion_intr_stall_en_falcon_stall_m(void) | ||
568 | { | ||
569 | return 0x1U << 2U; | ||
570 | } | ||
571 | static inline u32 minion_minion_intr_stall_en_falcon_stall_v(u32 r) | ||
572 | { | ||
573 | return (r >> 2U) & 0x1U; | ||
574 | } | ||
575 | static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_v(void) | ||
576 | { | ||
577 | return 0x00000001U; | ||
578 | } | ||
579 | static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_f(void) | ||
580 | { | ||
581 | return 0x4U; | ||
582 | } | ||
583 | static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_v(void) | ||
584 | { | ||
585 | return 0x00000000U; | ||
586 | } | ||
587 | static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_f(void) | ||
588 | { | ||
589 | return 0x0U; | ||
590 | } | ||
591 | static inline u32 minion_minion_intr_stall_en_falcon_nostall_f(u32 v) | ||
592 | { | ||
593 | return (v & 0x1U) << 3U; | ||
594 | } | ||
595 | static inline u32 minion_minion_intr_stall_en_falcon_nostall_m(void) | ||
596 | { | ||
597 | return 0x1U << 3U; | ||
598 | } | ||
599 | static inline u32 minion_minion_intr_stall_en_falcon_nostall_v(u32 r) | ||
600 | { | ||
601 | return (r >> 3U) & 0x1U; | ||
602 | } | ||
603 | static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_v(void) | ||
604 | { | ||
605 | return 0x00000001U; | ||
606 | } | ||
607 | static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_f(void) | ||
608 | { | ||
609 | return 0x8U; | ||
610 | } | ||
611 | static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_v(void) | ||
612 | { | ||
613 | return 0x00000000U; | ||
614 | } | ||
615 | static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_f(void) | ||
616 | { | ||
617 | return 0x0U; | ||
618 | } | ||
619 | static inline u32 minion_minion_intr_stall_en_link_f(u32 v) | ||
620 | { | ||
621 | return (v & 0xffffU) << 16U; | ||
622 | } | ||
623 | static inline u32 minion_minion_intr_stall_en_link_m(void) | ||
624 | { | ||
625 | return 0xffffU << 16U; | ||
626 | } | ||
627 | static inline u32 minion_minion_intr_stall_en_link_v(u32 r) | ||
628 | { | ||
629 | return (r >> 16U) & 0xffffU; | ||
630 | } | ||
631 | static inline u32 minion_nvlink_dl_cmd_r(u32 i) | ||
632 | { | ||
633 | return 0x00000900U + i*4U; | ||
634 | } | ||
635 | static inline u32 minion_nvlink_dl_cmd___size_1_v(void) | ||
636 | { | ||
637 | return 0x00000006U; | ||
638 | } | ||
639 | static inline u32 minion_nvlink_dl_cmd_command_f(u32 v) | ||
640 | { | ||
641 | return (v & 0xffU) << 0U; | ||
642 | } | ||
643 | static inline u32 minion_nvlink_dl_cmd_command_v(u32 r) | ||
644 | { | ||
645 | return (r >> 0U) & 0xffU; | ||
646 | } | ||
647 | static inline u32 minion_nvlink_dl_cmd_command_configeom_v(void) | ||
648 | { | ||
649 | return 0x00000040U; | ||
650 | } | ||
651 | static inline u32 minion_nvlink_dl_cmd_command_configeom_f(void) | ||
652 | { | ||
653 | return 0x40U; | ||
654 | } | ||
655 | static inline u32 minion_nvlink_dl_cmd_command_nop_v(void) | ||
656 | { | ||
657 | return 0x00000000U; | ||
658 | } | ||
659 | static inline u32 minion_nvlink_dl_cmd_command_nop_f(void) | ||
660 | { | ||
661 | return 0x0U; | ||
662 | } | ||
663 | static inline u32 minion_nvlink_dl_cmd_command_initphy_v(void) | ||
664 | { | ||
665 | return 0x00000001U; | ||
666 | } | ||
667 | static inline u32 minion_nvlink_dl_cmd_command_initphy_f(void) | ||
668 | { | ||
669 | return 0x1U; | ||
670 | } | ||
671 | static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_v(void) | ||
672 | { | ||
673 | return 0x00000003U; | ||
674 | } | ||
675 | static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_f(void) | ||
676 | { | ||
677 | return 0x3U; | ||
678 | } | ||
679 | static inline u32 minion_nvlink_dl_cmd_command_initdlpl_v(void) | ||
680 | { | ||
681 | return 0x00000004U; | ||
682 | } | ||
683 | static inline u32 minion_nvlink_dl_cmd_command_initdlpl_f(void) | ||
684 | { | ||
685 | return 0x4U; | ||
686 | } | ||
687 | static inline u32 minion_nvlink_dl_cmd_command_lanedisable_v(void) | ||
688 | { | ||
689 | return 0x00000008U; | ||
690 | } | ||
691 | static inline u32 minion_nvlink_dl_cmd_command_lanedisable_f(void) | ||
692 | { | ||
693 | return 0x8U; | ||
694 | } | ||
695 | static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_v(void) | ||
696 | { | ||
697 | return 0x00000009U; | ||
698 | } | ||
699 | static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_f(void) | ||
700 | { | ||
701 | return 0x9U; | ||
702 | } | ||
703 | static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_v(void) | ||
704 | { | ||
705 | return 0x0000000cU; | ||
706 | } | ||
707 | static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_f(void) | ||
708 | { | ||
709 | return 0xcU; | ||
710 | } | ||
711 | static inline u32 minion_nvlink_dl_cmd_command_setacmode_v(void) | ||
712 | { | ||
713 | return 0x0000000aU; | ||
714 | } | ||
715 | static inline u32 minion_nvlink_dl_cmd_command_setacmode_f(void) | ||
716 | { | ||
717 | return 0xaU; | ||
718 | } | ||
719 | static inline u32 minion_nvlink_dl_cmd_command_clracmode_v(void) | ||
720 | { | ||
721 | return 0x0000000bU; | ||
722 | } | ||
723 | static inline u32 minion_nvlink_dl_cmd_command_clracmode_f(void) | ||
724 | { | ||
725 | return 0xbU; | ||
726 | } | ||
727 | static inline u32 minion_nvlink_dl_cmd_command_enablepm_v(void) | ||
728 | { | ||
729 | return 0x00000010U; | ||
730 | } | ||
731 | static inline u32 minion_nvlink_dl_cmd_command_enablepm_f(void) | ||
732 | { | ||
733 | return 0x10U; | ||
734 | } | ||
735 | static inline u32 minion_nvlink_dl_cmd_command_disablepm_v(void) | ||
736 | { | ||
737 | return 0x00000011U; | ||
738 | } | ||
739 | static inline u32 minion_nvlink_dl_cmd_command_disablepm_f(void) | ||
740 | { | ||
741 | return 0x11U; | ||
742 | } | ||
743 | static inline u32 minion_nvlink_dl_cmd_command_savestate_v(void) | ||
744 | { | ||
745 | return 0x00000018U; | ||
746 | } | ||
747 | static inline u32 minion_nvlink_dl_cmd_command_savestate_f(void) | ||
748 | { | ||
749 | return 0x18U; | ||
750 | } | ||
751 | static inline u32 minion_nvlink_dl_cmd_command_restorestate_v(void) | ||
752 | { | ||
753 | return 0x00000019U; | ||
754 | } | ||
755 | static inline u32 minion_nvlink_dl_cmd_command_restorestate_f(void) | ||
756 | { | ||
757 | return 0x19U; | ||
758 | } | ||
759 | static inline u32 minion_nvlink_dl_cmd_command_initpll_0_v(void) | ||
760 | { | ||
761 | return 0x00000020U; | ||
762 | } | ||
763 | static inline u32 minion_nvlink_dl_cmd_command_initpll_0_f(void) | ||
764 | { | ||
765 | return 0x20U; | ||
766 | } | ||
767 | static inline u32 minion_nvlink_dl_cmd_command_initpll_1_v(void) | ||
768 | { | ||
769 | return 0x00000021U; | ||
770 | } | ||
771 | static inline u32 minion_nvlink_dl_cmd_command_initpll_1_f(void) | ||
772 | { | ||
773 | return 0x21U; | ||
774 | } | ||
775 | static inline u32 minion_nvlink_dl_cmd_command_initpll_2_v(void) | ||
776 | { | ||
777 | return 0x00000022U; | ||
778 | } | ||
779 | static inline u32 minion_nvlink_dl_cmd_command_initpll_2_f(void) | ||
780 | { | ||
781 | return 0x22U; | ||
782 | } | ||
783 | static inline u32 minion_nvlink_dl_cmd_command_initpll_3_v(void) | ||
784 | { | ||
785 | return 0x00000023U; | ||
786 | } | ||
787 | static inline u32 minion_nvlink_dl_cmd_command_initpll_3_f(void) | ||
788 | { | ||
789 | return 0x23U; | ||
790 | } | ||
791 | static inline u32 minion_nvlink_dl_cmd_command_initpll_4_v(void) | ||
792 | { | ||
793 | return 0x00000024U; | ||
794 | } | ||
795 | static inline u32 minion_nvlink_dl_cmd_command_initpll_4_f(void) | ||
796 | { | ||
797 | return 0x24U; | ||
798 | } | ||
799 | static inline u32 minion_nvlink_dl_cmd_command_initpll_5_v(void) | ||
800 | { | ||
801 | return 0x00000025U; | ||
802 | } | ||
803 | static inline u32 minion_nvlink_dl_cmd_command_initpll_5_f(void) | ||
804 | { | ||
805 | return 0x25U; | ||
806 | } | ||
807 | static inline u32 minion_nvlink_dl_cmd_command_initpll_6_v(void) | ||
808 | { | ||
809 | return 0x00000026U; | ||
810 | } | ||
811 | static inline u32 minion_nvlink_dl_cmd_command_initpll_6_f(void) | ||
812 | { | ||
813 | return 0x26U; | ||
814 | } | ||
815 | static inline u32 minion_nvlink_dl_cmd_command_initpll_7_v(void) | ||
816 | { | ||
817 | return 0x00000027U; | ||
818 | } | ||
819 | static inline u32 minion_nvlink_dl_cmd_command_initpll_7_f(void) | ||
820 | { | ||
821 | return 0x27U; | ||
822 | } | ||
823 | static inline u32 minion_nvlink_dl_cmd_fault_f(u32 v) | ||
824 | { | ||
825 | return (v & 0x1U) << 30U; | ||
826 | } | ||
827 | static inline u32 minion_nvlink_dl_cmd_fault_v(u32 r) | ||
828 | { | ||
829 | return (r >> 30U) & 0x1U; | ||
830 | } | ||
831 | static inline u32 minion_nvlink_dl_cmd_ready_f(u32 v) | ||
832 | { | ||
833 | return (v & 0x1U) << 31U; | ||
834 | } | ||
835 | static inline u32 minion_nvlink_dl_cmd_ready_v(u32 r) | ||
836 | { | ||
837 | return (r >> 31U) & 0x1U; | ||
838 | } | ||
839 | static inline u32 minion_misc_0_r(void) | ||
840 | { | ||
841 | return 0x000008b0U; | ||
842 | } | ||
843 | static inline u32 minion_misc_0_scratch_swrw_0_f(u32 v) | ||
844 | { | ||
845 | return (v & 0xffffffffU) << 0U; | ||
846 | } | ||
847 | static inline u32 minion_misc_0_scratch_swrw_0_v(u32 r) | ||
848 | { | ||
849 | return (r >> 0U) & 0xffffffffU; | ||
850 | } | ||
851 | static inline u32 minion_nvlink_link_intr_r(u32 i) | ||
852 | { | ||
853 | return 0x00000a00U + i*4U; | ||
854 | } | ||
855 | static inline u32 minion_nvlink_link_intr___size_1_v(void) | ||
856 | { | ||
857 | return 0x00000006U; | ||
858 | } | ||
859 | static inline u32 minion_nvlink_link_intr_code_f(u32 v) | ||
860 | { | ||
861 | return (v & 0xffU) << 0U; | ||
862 | } | ||
863 | static inline u32 minion_nvlink_link_intr_code_m(void) | ||
864 | { | ||
865 | return 0xffU << 0U; | ||
866 | } | ||
867 | static inline u32 minion_nvlink_link_intr_code_v(u32 r) | ||
868 | { | ||
869 | return (r >> 0U) & 0xffU; | ||
870 | } | ||
871 | static inline u32 minion_nvlink_link_intr_code_na_v(void) | ||
872 | { | ||
873 | return 0x00000000U; | ||
874 | } | ||
875 | static inline u32 minion_nvlink_link_intr_code_na_f(void) | ||
876 | { | ||
877 | return 0x0U; | ||
878 | } | ||
879 | static inline u32 minion_nvlink_link_intr_code_swreq_v(void) | ||
880 | { | ||
881 | return 0x00000001U; | ||
882 | } | ||
883 | static inline u32 minion_nvlink_link_intr_code_swreq_f(void) | ||
884 | { | ||
885 | return 0x1U; | ||
886 | } | ||
887 | static inline u32 minion_nvlink_link_intr_code_dlreq_v(void) | ||
888 | { | ||
889 | return 0x00000002U; | ||
890 | } | ||
891 | static inline u32 minion_nvlink_link_intr_code_dlreq_f(void) | ||
892 | { | ||
893 | return 0x2U; | ||
894 | } | ||
895 | static inline u32 minion_nvlink_link_intr_subcode_f(u32 v) | ||
896 | { | ||
897 | return (v & 0xffU) << 8U; | ||
898 | } | ||
899 | static inline u32 minion_nvlink_link_intr_subcode_m(void) | ||
900 | { | ||
901 | return 0xffU << 8U; | ||
902 | } | ||
903 | static inline u32 minion_nvlink_link_intr_subcode_v(u32 r) | ||
904 | { | ||
905 | return (r >> 8U) & 0xffU; | ||
906 | } | ||
907 | static inline u32 minion_nvlink_link_intr_state_f(u32 v) | ||
908 | { | ||
909 | return (v & 0x1U) << 31U; | ||
910 | } | ||
911 | static inline u32 minion_nvlink_link_intr_state_m(void) | ||
912 | { | ||
913 | return 0x1U << 31U; | ||
914 | } | ||
915 | static inline u32 minion_nvlink_link_intr_state_v(u32 r) | ||
916 | { | ||
917 | return (r >> 31U) & 0x1U; | ||
918 | } | ||
919 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h new file mode 100644 index 00000000..2e4ec168 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h | |||
@@ -0,0 +1,1571 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_nvl_gv100_h_ | ||
57 | #define _hw_nvl_gv100_h_ | ||
58 | |||
59 | static inline u32 nvl_link_state_r(void) | ||
60 | { | ||
61 | return 0x00000000U; | ||
62 | } | ||
63 | static inline u32 nvl_link_state_state_f(u32 v) | ||
64 | { | ||
65 | return (v & 0xffU) << 0U; | ||
66 | } | ||
67 | static inline u32 nvl_link_state_state_m(void) | ||
68 | { | ||
69 | return 0xffU << 0U; | ||
70 | } | ||
71 | static inline u32 nvl_link_state_state_v(u32 r) | ||
72 | { | ||
73 | return (r >> 0U) & 0xffU; | ||
74 | } | ||
75 | static inline u32 nvl_link_state_state_init_v(void) | ||
76 | { | ||
77 | return 0x00000000U; | ||
78 | } | ||
79 | static inline u32 nvl_link_state_state_init_f(void) | ||
80 | { | ||
81 | return 0x0U; | ||
82 | } | ||
83 | static inline u32 nvl_link_state_state_hwcfg_v(void) | ||
84 | { | ||
85 | return 0x00000001U; | ||
86 | } | ||
87 | static inline u32 nvl_link_state_state_hwcfg_f(void) | ||
88 | { | ||
89 | return 0x1U; | ||
90 | } | ||
91 | static inline u32 nvl_link_state_state_swcfg_v(void) | ||
92 | { | ||
93 | return 0x00000002U; | ||
94 | } | ||
95 | static inline u32 nvl_link_state_state_swcfg_f(void) | ||
96 | { | ||
97 | return 0x2U; | ||
98 | } | ||
99 | static inline u32 nvl_link_state_state_active_v(void) | ||
100 | { | ||
101 | return 0x00000003U; | ||
102 | } | ||
103 | static inline u32 nvl_link_state_state_active_f(void) | ||
104 | { | ||
105 | return 0x3U; | ||
106 | } | ||
107 | static inline u32 nvl_link_state_state_fault_v(void) | ||
108 | { | ||
109 | return 0x00000004U; | ||
110 | } | ||
111 | static inline u32 nvl_link_state_state_fault_f(void) | ||
112 | { | ||
113 | return 0x4U; | ||
114 | } | ||
115 | static inline u32 nvl_link_state_state_rcvy_ac_v(void) | ||
116 | { | ||
117 | return 0x00000008U; | ||
118 | } | ||
119 | static inline u32 nvl_link_state_state_rcvy_ac_f(void) | ||
120 | { | ||
121 | return 0x8U; | ||
122 | } | ||
123 | static inline u32 nvl_link_state_state_rcvy_sw_v(void) | ||
124 | { | ||
125 | return 0x00000009U; | ||
126 | } | ||
127 | static inline u32 nvl_link_state_state_rcvy_sw_f(void) | ||
128 | { | ||
129 | return 0x9U; | ||
130 | } | ||
131 | static inline u32 nvl_link_state_state_rcvy_rx_v(void) | ||
132 | { | ||
133 | return 0x0000000aU; | ||
134 | } | ||
135 | static inline u32 nvl_link_state_state_rcvy_rx_f(void) | ||
136 | { | ||
137 | return 0xaU; | ||
138 | } | ||
139 | static inline u32 nvl_link_state_an0_busy_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 12U; | ||
142 | } | ||
143 | static inline u32 nvl_link_state_an0_busy_m(void) | ||
144 | { | ||
145 | return 0x1U << 12U; | ||
146 | } | ||
147 | static inline u32 nvl_link_state_an0_busy_v(u32 r) | ||
148 | { | ||
149 | return (r >> 12U) & 0x1U; | ||
150 | } | ||
151 | static inline u32 nvl_link_state_tl_busy_f(u32 v) | ||
152 | { | ||
153 | return (v & 0x1U) << 13U; | ||
154 | } | ||
155 | static inline u32 nvl_link_state_tl_busy_m(void) | ||
156 | { | ||
157 | return 0x1U << 13U; | ||
158 | } | ||
159 | static inline u32 nvl_link_state_tl_busy_v(u32 r) | ||
160 | { | ||
161 | return (r >> 13U) & 0x1U; | ||
162 | } | ||
163 | static inline u32 nvl_link_state_dbg_substate_f(u32 v) | ||
164 | { | ||
165 | return (v & 0xffffU) << 16U; | ||
166 | } | ||
167 | static inline u32 nvl_link_state_dbg_substate_m(void) | ||
168 | { | ||
169 | return 0xffffU << 16U; | ||
170 | } | ||
171 | static inline u32 nvl_link_state_dbg_substate_v(u32 r) | ||
172 | { | ||
173 | return (r >> 16U) & 0xffffU; | ||
174 | } | ||
175 | static inline u32 nvl_link_activity_r(void) | ||
176 | { | ||
177 | return 0x0000000cU; | ||
178 | } | ||
179 | static inline u32 nvl_link_activity_blkact_f(u32 v) | ||
180 | { | ||
181 | return (v & 0x7U) << 0U; | ||
182 | } | ||
183 | static inline u32 nvl_link_activity_blkact_m(void) | ||
184 | { | ||
185 | return 0x7U << 0U; | ||
186 | } | ||
187 | static inline u32 nvl_link_activity_blkact_v(u32 r) | ||
188 | { | ||
189 | return (r >> 0U) & 0x7U; | ||
190 | } | ||
191 | static inline u32 nvl_sublink_activity_r(u32 i) | ||
192 | { | ||
193 | return 0x00000010U + i*4U; | ||
194 | } | ||
195 | static inline u32 nvl_sublink_activity_blkact0_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x7U) << 0U; | ||
198 | } | ||
199 | static inline u32 nvl_sublink_activity_blkact0_m(void) | ||
200 | { | ||
201 | return 0x7U << 0U; | ||
202 | } | ||
203 | static inline u32 nvl_sublink_activity_blkact0_v(u32 r) | ||
204 | { | ||
205 | return (r >> 0U) & 0x7U; | ||
206 | } | ||
207 | static inline u32 nvl_sublink_activity_blkact1_f(u32 v) | ||
208 | { | ||
209 | return (v & 0x7U) << 8U; | ||
210 | } | ||
211 | static inline u32 nvl_sublink_activity_blkact1_m(void) | ||
212 | { | ||
213 | return 0x7U << 8U; | ||
214 | } | ||
215 | static inline u32 nvl_sublink_activity_blkact1_v(u32 r) | ||
216 | { | ||
217 | return (r >> 8U) & 0x7U; | ||
218 | } | ||
219 | static inline u32 nvl_link_config_r(void) | ||
220 | { | ||
221 | return 0x00000018U; | ||
222 | } | ||
223 | static inline u32 nvl_link_config_ac_safe_en_f(u32 v) | ||
224 | { | ||
225 | return (v & 0x1U) << 30U; | ||
226 | } | ||
227 | static inline u32 nvl_link_config_ac_safe_en_m(void) | ||
228 | { | ||
229 | return 0x1U << 30U; | ||
230 | } | ||
231 | static inline u32 nvl_link_config_ac_safe_en_v(u32 r) | ||
232 | { | ||
233 | return (r >> 30U) & 0x1U; | ||
234 | } | ||
235 | static inline u32 nvl_link_config_ac_safe_en_on_v(void) | ||
236 | { | ||
237 | return 0x00000001U; | ||
238 | } | ||
239 | static inline u32 nvl_link_config_ac_safe_en_on_f(void) | ||
240 | { | ||
241 | return 0x40000000U; | ||
242 | } | ||
243 | static inline u32 nvl_link_config_link_en_f(u32 v) | ||
244 | { | ||
245 | return (v & 0x1U) << 31U; | ||
246 | } | ||
247 | static inline u32 nvl_link_config_link_en_m(void) | ||
248 | { | ||
249 | return 0x1U << 31U; | ||
250 | } | ||
251 | static inline u32 nvl_link_config_link_en_v(u32 r) | ||
252 | { | ||
253 | return (r >> 31U) & 0x1U; | ||
254 | } | ||
255 | static inline u32 nvl_link_config_link_en_on_v(void) | ||
256 | { | ||
257 | return 0x00000001U; | ||
258 | } | ||
259 | static inline u32 nvl_link_config_link_en_on_f(void) | ||
260 | { | ||
261 | return 0x80000000U; | ||
262 | } | ||
263 | static inline u32 nvl_link_change_r(void) | ||
264 | { | ||
265 | return 0x00000040U; | ||
266 | } | ||
267 | static inline u32 nvl_link_change_oldstate_mask_f(u32 v) | ||
268 | { | ||
269 | return (v & 0xfU) << 16U; | ||
270 | } | ||
271 | static inline u32 nvl_link_change_oldstate_mask_m(void) | ||
272 | { | ||
273 | return 0xfU << 16U; | ||
274 | } | ||
275 | static inline u32 nvl_link_change_oldstate_mask_v(u32 r) | ||
276 | { | ||
277 | return (r >> 16U) & 0xfU; | ||
278 | } | ||
279 | static inline u32 nvl_link_change_oldstate_mask_dontcare_v(void) | ||
280 | { | ||
281 | return 0x0000000fU; | ||
282 | } | ||
283 | static inline u32 nvl_link_change_oldstate_mask_dontcare_f(void) | ||
284 | { | ||
285 | return 0xf0000U; | ||
286 | } | ||
287 | static inline u32 nvl_link_change_newstate_f(u32 v) | ||
288 | { | ||
289 | return (v & 0xfU) << 4U; | ||
290 | } | ||
291 | static inline u32 nvl_link_change_newstate_m(void) | ||
292 | { | ||
293 | return 0xfU << 4U; | ||
294 | } | ||
295 | static inline u32 nvl_link_change_newstate_v(u32 r) | ||
296 | { | ||
297 | return (r >> 4U) & 0xfU; | ||
298 | } | ||
299 | static inline u32 nvl_link_change_newstate_hwcfg_v(void) | ||
300 | { | ||
301 | return 0x00000001U; | ||
302 | } | ||
303 | static inline u32 nvl_link_change_newstate_hwcfg_f(void) | ||
304 | { | ||
305 | return 0x10U; | ||
306 | } | ||
307 | static inline u32 nvl_link_change_newstate_swcfg_v(void) | ||
308 | { | ||
309 | return 0x00000002U; | ||
310 | } | ||
311 | static inline u32 nvl_link_change_newstate_swcfg_f(void) | ||
312 | { | ||
313 | return 0x20U; | ||
314 | } | ||
315 | static inline u32 nvl_link_change_newstate_active_v(void) | ||
316 | { | ||
317 | return 0x00000003U; | ||
318 | } | ||
319 | static inline u32 nvl_link_change_newstate_active_f(void) | ||
320 | { | ||
321 | return 0x30U; | ||
322 | } | ||
323 | static inline u32 nvl_link_change_action_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x3U) << 2U; | ||
326 | } | ||
327 | static inline u32 nvl_link_change_action_m(void) | ||
328 | { | ||
329 | return 0x3U << 2U; | ||
330 | } | ||
331 | static inline u32 nvl_link_change_action_v(u32 r) | ||
332 | { | ||
333 | return (r >> 2U) & 0x3U; | ||
334 | } | ||
335 | static inline u32 nvl_link_change_action_ltssm_change_v(void) | ||
336 | { | ||
337 | return 0x00000001U; | ||
338 | } | ||
339 | static inline u32 nvl_link_change_action_ltssm_change_f(void) | ||
340 | { | ||
341 | return 0x4U; | ||
342 | } | ||
343 | static inline u32 nvl_link_change_status_f(u32 v) | ||
344 | { | ||
345 | return (v & 0x3U) << 0U; | ||
346 | } | ||
347 | static inline u32 nvl_link_change_status_m(void) | ||
348 | { | ||
349 | return 0x3U << 0U; | ||
350 | } | ||
351 | static inline u32 nvl_link_change_status_v(u32 r) | ||
352 | { | ||
353 | return (r >> 0U) & 0x3U; | ||
354 | } | ||
355 | static inline u32 nvl_link_change_status_done_v(void) | ||
356 | { | ||
357 | return 0x00000000U; | ||
358 | } | ||
359 | static inline u32 nvl_link_change_status_done_f(void) | ||
360 | { | ||
361 | return 0x0U; | ||
362 | } | ||
363 | static inline u32 nvl_link_change_status_busy_v(void) | ||
364 | { | ||
365 | return 0x00000001U; | ||
366 | } | ||
367 | static inline u32 nvl_link_change_status_busy_f(void) | ||
368 | { | ||
369 | return 0x1U; | ||
370 | } | ||
371 | static inline u32 nvl_link_change_status_fault_v(void) | ||
372 | { | ||
373 | return 0x00000002U; | ||
374 | } | ||
375 | static inline u32 nvl_link_change_status_fault_f(void) | ||
376 | { | ||
377 | return 0x2U; | ||
378 | } | ||
379 | static inline u32 nvl_sublink_change_r(void) | ||
380 | { | ||
381 | return 0x00000044U; | ||
382 | } | ||
383 | static inline u32 nvl_sublink_change_countdown_f(u32 v) | ||
384 | { | ||
385 | return (v & 0xfffU) << 20U; | ||
386 | } | ||
387 | static inline u32 nvl_sublink_change_countdown_m(void) | ||
388 | { | ||
389 | return 0xfffU << 20U; | ||
390 | } | ||
391 | static inline u32 nvl_sublink_change_countdown_v(u32 r) | ||
392 | { | ||
393 | return (r >> 20U) & 0xfffU; | ||
394 | } | ||
395 | static inline u32 nvl_sublink_change_oldstate_mask_f(u32 v) | ||
396 | { | ||
397 | return (v & 0xfU) << 16U; | ||
398 | } | ||
399 | static inline u32 nvl_sublink_change_oldstate_mask_m(void) | ||
400 | { | ||
401 | return 0xfU << 16U; | ||
402 | } | ||
403 | static inline u32 nvl_sublink_change_oldstate_mask_v(u32 r) | ||
404 | { | ||
405 | return (r >> 16U) & 0xfU; | ||
406 | } | ||
407 | static inline u32 nvl_sublink_change_oldstate_mask_dontcare_v(void) | ||
408 | { | ||
409 | return 0x0000000fU; | ||
410 | } | ||
411 | static inline u32 nvl_sublink_change_oldstate_mask_dontcare_f(void) | ||
412 | { | ||
413 | return 0xf0000U; | ||
414 | } | ||
415 | static inline u32 nvl_sublink_change_sublink_f(u32 v) | ||
416 | { | ||
417 | return (v & 0xfU) << 12U; | ||
418 | } | ||
419 | static inline u32 nvl_sublink_change_sublink_m(void) | ||
420 | { | ||
421 | return 0xfU << 12U; | ||
422 | } | ||
423 | static inline u32 nvl_sublink_change_sublink_v(u32 r) | ||
424 | { | ||
425 | return (r >> 12U) & 0xfU; | ||
426 | } | ||
427 | static inline u32 nvl_sublink_change_sublink_tx_v(void) | ||
428 | { | ||
429 | return 0x00000000U; | ||
430 | } | ||
431 | static inline u32 nvl_sublink_change_sublink_tx_f(void) | ||
432 | { | ||
433 | return 0x0U; | ||
434 | } | ||
435 | static inline u32 nvl_sublink_change_sublink_rx_v(void) | ||
436 | { | ||
437 | return 0x00000001U; | ||
438 | } | ||
439 | static inline u32 nvl_sublink_change_sublink_rx_f(void) | ||
440 | { | ||
441 | return 0x1000U; | ||
442 | } | ||
443 | static inline u32 nvl_sublink_change_newstate_f(u32 v) | ||
444 | { | ||
445 | return (v & 0xfU) << 4U; | ||
446 | } | ||
447 | static inline u32 nvl_sublink_change_newstate_m(void) | ||
448 | { | ||
449 | return 0xfU << 4U; | ||
450 | } | ||
451 | static inline u32 nvl_sublink_change_newstate_v(u32 r) | ||
452 | { | ||
453 | return (r >> 4U) & 0xfU; | ||
454 | } | ||
455 | static inline u32 nvl_sublink_change_newstate_hs_v(void) | ||
456 | { | ||
457 | return 0x00000000U; | ||
458 | } | ||
459 | static inline u32 nvl_sublink_change_newstate_hs_f(void) | ||
460 | { | ||
461 | return 0x0U; | ||
462 | } | ||
463 | static inline u32 nvl_sublink_change_newstate_eighth_v(void) | ||
464 | { | ||
465 | return 0x00000004U; | ||
466 | } | ||
467 | static inline u32 nvl_sublink_change_newstate_eighth_f(void) | ||
468 | { | ||
469 | return 0x40U; | ||
470 | } | ||
471 | static inline u32 nvl_sublink_change_newstate_train_v(void) | ||
472 | { | ||
473 | return 0x00000005U; | ||
474 | } | ||
475 | static inline u32 nvl_sublink_change_newstate_train_f(void) | ||
476 | { | ||
477 | return 0x50U; | ||
478 | } | ||
479 | static inline u32 nvl_sublink_change_newstate_safe_v(void) | ||
480 | { | ||
481 | return 0x00000006U; | ||
482 | } | ||
483 | static inline u32 nvl_sublink_change_newstate_safe_f(void) | ||
484 | { | ||
485 | return 0x60U; | ||
486 | } | ||
487 | static inline u32 nvl_sublink_change_newstate_off_v(void) | ||
488 | { | ||
489 | return 0x00000007U; | ||
490 | } | ||
491 | static inline u32 nvl_sublink_change_newstate_off_f(void) | ||
492 | { | ||
493 | return 0x70U; | ||
494 | } | ||
495 | static inline u32 nvl_sublink_change_action_f(u32 v) | ||
496 | { | ||
497 | return (v & 0x3U) << 2U; | ||
498 | } | ||
499 | static inline u32 nvl_sublink_change_action_m(void) | ||
500 | { | ||
501 | return 0x3U << 2U; | ||
502 | } | ||
503 | static inline u32 nvl_sublink_change_action_v(u32 r) | ||
504 | { | ||
505 | return (r >> 2U) & 0x3U; | ||
506 | } | ||
507 | static inline u32 nvl_sublink_change_action_slsm_change_v(void) | ||
508 | { | ||
509 | return 0x00000001U; | ||
510 | } | ||
511 | static inline u32 nvl_sublink_change_action_slsm_change_f(void) | ||
512 | { | ||
513 | return 0x4U; | ||
514 | } | ||
515 | static inline u32 nvl_sublink_change_status_f(u32 v) | ||
516 | { | ||
517 | return (v & 0x3U) << 0U; | ||
518 | } | ||
519 | static inline u32 nvl_sublink_change_status_m(void) | ||
520 | { | ||
521 | return 0x3U << 0U; | ||
522 | } | ||
523 | static inline u32 nvl_sublink_change_status_v(u32 r) | ||
524 | { | ||
525 | return (r >> 0U) & 0x3U; | ||
526 | } | ||
527 | static inline u32 nvl_sublink_change_status_done_v(void) | ||
528 | { | ||
529 | return 0x00000000U; | ||
530 | } | ||
531 | static inline u32 nvl_sublink_change_status_done_f(void) | ||
532 | { | ||
533 | return 0x0U; | ||
534 | } | ||
535 | static inline u32 nvl_sublink_change_status_busy_v(void) | ||
536 | { | ||
537 | return 0x00000001U; | ||
538 | } | ||
539 | static inline u32 nvl_sublink_change_status_busy_f(void) | ||
540 | { | ||
541 | return 0x1U; | ||
542 | } | ||
543 | static inline u32 nvl_sublink_change_status_fault_v(void) | ||
544 | { | ||
545 | return 0x00000002U; | ||
546 | } | ||
547 | static inline u32 nvl_sublink_change_status_fault_f(void) | ||
548 | { | ||
549 | return 0x2U; | ||
550 | } | ||
551 | static inline u32 nvl_link_test_r(void) | ||
552 | { | ||
553 | return 0x00000048U; | ||
554 | } | ||
555 | static inline u32 nvl_link_test_mode_f(u32 v) | ||
556 | { | ||
557 | return (v & 0x1U) << 0U; | ||
558 | } | ||
559 | static inline u32 nvl_link_test_mode_m(void) | ||
560 | { | ||
561 | return 0x1U << 0U; | ||
562 | } | ||
563 | static inline u32 nvl_link_test_mode_v(u32 r) | ||
564 | { | ||
565 | return (r >> 0U) & 0x1U; | ||
566 | } | ||
567 | static inline u32 nvl_link_test_mode_enable_v(void) | ||
568 | { | ||
569 | return 0x00000001U; | ||
570 | } | ||
571 | static inline u32 nvl_link_test_mode_enable_f(void) | ||
572 | { | ||
573 | return 0x1U; | ||
574 | } | ||
575 | static inline u32 nvl_link_test_auto_hwcfg_f(u32 v) | ||
576 | { | ||
577 | return (v & 0x1U) << 30U; | ||
578 | } | ||
579 | static inline u32 nvl_link_test_auto_hwcfg_m(void) | ||
580 | { | ||
581 | return 0x1U << 30U; | ||
582 | } | ||
583 | static inline u32 nvl_link_test_auto_hwcfg_v(u32 r) | ||
584 | { | ||
585 | return (r >> 30U) & 0x1U; | ||
586 | } | ||
587 | static inline u32 nvl_link_test_auto_hwcfg_enable_v(void) | ||
588 | { | ||
589 | return 0x00000001U; | ||
590 | } | ||
591 | static inline u32 nvl_link_test_auto_hwcfg_enable_f(void) | ||
592 | { | ||
593 | return 0x40000000U; | ||
594 | } | ||
595 | static inline u32 nvl_link_test_auto_nvhs_f(u32 v) | ||
596 | { | ||
597 | return (v & 0x1U) << 31U; | ||
598 | } | ||
599 | static inline u32 nvl_link_test_auto_nvhs_m(void) | ||
600 | { | ||
601 | return 0x1U << 31U; | ||
602 | } | ||
603 | static inline u32 nvl_link_test_auto_nvhs_v(u32 r) | ||
604 | { | ||
605 | return (r >> 31U) & 0x1U; | ||
606 | } | ||
607 | static inline u32 nvl_link_test_auto_nvhs_enable_v(void) | ||
608 | { | ||
609 | return 0x00000001U; | ||
610 | } | ||
611 | static inline u32 nvl_link_test_auto_nvhs_enable_f(void) | ||
612 | { | ||
613 | return 0x80000000U; | ||
614 | } | ||
615 | static inline u32 nvl_sl0_slsm_status_tx_r(void) | ||
616 | { | ||
617 | return 0x00002024U; | ||
618 | } | ||
619 | static inline u32 nvl_sl0_slsm_status_tx_substate_f(u32 v) | ||
620 | { | ||
621 | return (v & 0xfU) << 0U; | ||
622 | } | ||
623 | static inline u32 nvl_sl0_slsm_status_tx_substate_m(void) | ||
624 | { | ||
625 | return 0xfU << 0U; | ||
626 | } | ||
627 | static inline u32 nvl_sl0_slsm_status_tx_substate_v(u32 r) | ||
628 | { | ||
629 | return (r >> 0U) & 0xfU; | ||
630 | } | ||
631 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_f(u32 v) | ||
632 | { | ||
633 | return (v & 0xfU) << 4U; | ||
634 | } | ||
635 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_m(void) | ||
636 | { | ||
637 | return 0xfU << 4U; | ||
638 | } | ||
639 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_v(u32 r) | ||
640 | { | ||
641 | return (r >> 4U) & 0xfU; | ||
642 | } | ||
643 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_v(void) | ||
644 | { | ||
645 | return 0x00000000U; | ||
646 | } | ||
647 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_f(void) | ||
648 | { | ||
649 | return 0x0U; | ||
650 | } | ||
651 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_v(void) | ||
652 | { | ||
653 | return 0x00000004U; | ||
654 | } | ||
655 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_f(void) | ||
656 | { | ||
657 | return 0x40U; | ||
658 | } | ||
659 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_v(void) | ||
660 | { | ||
661 | return 0x00000005U; | ||
662 | } | ||
663 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_f(void) | ||
664 | { | ||
665 | return 0x50U; | ||
666 | } | ||
667 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_v(void) | ||
668 | { | ||
669 | return 0x00000007U; | ||
670 | } | ||
671 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_f(void) | ||
672 | { | ||
673 | return 0x70U; | ||
674 | } | ||
675 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_v(void) | ||
676 | { | ||
677 | return 0x00000006U; | ||
678 | } | ||
679 | static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_f(void) | ||
680 | { | ||
681 | return 0x60U; | ||
682 | } | ||
683 | static inline u32 nvl_sl1_slsm_status_rx_r(void) | ||
684 | { | ||
685 | return 0x00003014U; | ||
686 | } | ||
687 | static inline u32 nvl_sl1_slsm_status_rx_substate_f(u32 v) | ||
688 | { | ||
689 | return (v & 0xfU) << 0U; | ||
690 | } | ||
691 | static inline u32 nvl_sl1_slsm_status_rx_substate_m(void) | ||
692 | { | ||
693 | return 0xfU << 0U; | ||
694 | } | ||
695 | static inline u32 nvl_sl1_slsm_status_rx_substate_v(u32 r) | ||
696 | { | ||
697 | return (r >> 0U) & 0xfU; | ||
698 | } | ||
699 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_f(u32 v) | ||
700 | { | ||
701 | return (v & 0xfU) << 4U; | ||
702 | } | ||
703 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_m(void) | ||
704 | { | ||
705 | return 0xfU << 4U; | ||
706 | } | ||
707 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_v(u32 r) | ||
708 | { | ||
709 | return (r >> 4U) & 0xfU; | ||
710 | } | ||
711 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_v(void) | ||
712 | { | ||
713 | return 0x00000000U; | ||
714 | } | ||
715 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_f(void) | ||
716 | { | ||
717 | return 0x0U; | ||
718 | } | ||
719 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_v(void) | ||
720 | { | ||
721 | return 0x00000004U; | ||
722 | } | ||
723 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_f(void) | ||
724 | { | ||
725 | return 0x40U; | ||
726 | } | ||
727 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_v(void) | ||
728 | { | ||
729 | return 0x00000005U; | ||
730 | } | ||
731 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_f(void) | ||
732 | { | ||
733 | return 0x50U; | ||
734 | } | ||
735 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_v(void) | ||
736 | { | ||
737 | return 0x00000007U; | ||
738 | } | ||
739 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_f(void) | ||
740 | { | ||
741 | return 0x70U; | ||
742 | } | ||
743 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_v(void) | ||
744 | { | ||
745 | return 0x00000006U; | ||
746 | } | ||
747 | static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_f(void) | ||
748 | { | ||
749 | return 0x60U; | ||
750 | } | ||
751 | static inline u32 nvl_sl0_safe_ctrl2_tx_r(void) | ||
752 | { | ||
753 | return 0x00002008U; | ||
754 | } | ||
755 | static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_f(u32 v) | ||
756 | { | ||
757 | return (v & 0x7ffU) << 0U; | ||
758 | } | ||
759 | static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_m(void) | ||
760 | { | ||
761 | return 0x7ffU << 0U; | ||
762 | } | ||
763 | static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_v(u32 r) | ||
764 | { | ||
765 | return (r >> 0U) & 0x7ffU; | ||
766 | } | ||
767 | static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_v(void) | ||
768 | { | ||
769 | return 0x00000728U; | ||
770 | } | ||
771 | static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_f(void) | ||
772 | { | ||
773 | return 0x728U; | ||
774 | } | ||
775 | static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(u32 v) | ||
776 | { | ||
777 | return (v & 0x1fU) << 11U; | ||
778 | } | ||
779 | static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(void) | ||
780 | { | ||
781 | return 0x1fU << 11U; | ||
782 | } | ||
783 | static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(u32 r) | ||
784 | { | ||
785 | return (r >> 11U) & 0x1fU; | ||
786 | } | ||
787 | static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v(void) | ||
788 | { | ||
789 | return 0x0000000fU; | ||
790 | } | ||
791 | static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f(void) | ||
792 | { | ||
793 | return 0x7800U; | ||
794 | } | ||
795 | static inline u32 nvl_sl1_error_rate_ctrl_r(void) | ||
796 | { | ||
797 | return 0x00003284U; | ||
798 | } | ||
799 | static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_f(u32 v) | ||
800 | { | ||
801 | return (v & 0x7U) << 0U; | ||
802 | } | ||
803 | static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_m(void) | ||
804 | { | ||
805 | return 0x7U << 0U; | ||
806 | } | ||
807 | static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_v(u32 r) | ||
808 | { | ||
809 | return (r >> 0U) & 0x7U; | ||
810 | } | ||
811 | static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_f(u32 v) | ||
812 | { | ||
813 | return (v & 0x7U) << 16U; | ||
814 | } | ||
815 | static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_m(void) | ||
816 | { | ||
817 | return 0x7U << 16U; | ||
818 | } | ||
819 | static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_v(u32 r) | ||
820 | { | ||
821 | return (r >> 16U) & 0x7U; | ||
822 | } | ||
823 | static inline u32 nvl_sl1_rxslsm_timeout_2_r(void) | ||
824 | { | ||
825 | return 0x00003034U; | ||
826 | } | ||
827 | static inline u32 nvl_txiobist_configreg_r(void) | ||
828 | { | ||
829 | return 0x00002e14U; | ||
830 | } | ||
831 | static inline u32 nvl_txiobist_configreg_io_bist_mode_in_f(u32 v) | ||
832 | { | ||
833 | return (v & 0x1U) << 17U; | ||
834 | } | ||
835 | static inline u32 nvl_txiobist_configreg_io_bist_mode_in_m(void) | ||
836 | { | ||
837 | return 0x1U << 17U; | ||
838 | } | ||
839 | static inline u32 nvl_txiobist_configreg_io_bist_mode_in_v(u32 r) | ||
840 | { | ||
841 | return (r >> 17U) & 0x1U; | ||
842 | } | ||
843 | static inline u32 nvl_txiobist_config_r(void) | ||
844 | { | ||
845 | return 0x00002e10U; | ||
846 | } | ||
847 | static inline u32 nvl_txiobist_config_dpg_prbsseedld_f(u32 v) | ||
848 | { | ||
849 | return (v & 0x1U) << 2U; | ||
850 | } | ||
851 | static inline u32 nvl_txiobist_config_dpg_prbsseedld_m(void) | ||
852 | { | ||
853 | return 0x1U << 2U; | ||
854 | } | ||
855 | static inline u32 nvl_txiobist_config_dpg_prbsseedld_v(u32 r) | ||
856 | { | ||
857 | return (r >> 2U) & 0x1U; | ||
858 | } | ||
859 | static inline u32 nvl_intr_r(void) | ||
860 | { | ||
861 | return 0x00000050U; | ||
862 | } | ||
863 | static inline u32 nvl_intr_tx_replay_f(u32 v) | ||
864 | { | ||
865 | return (v & 0x1U) << 0U; | ||
866 | } | ||
867 | static inline u32 nvl_intr_tx_replay_m(void) | ||
868 | { | ||
869 | return 0x1U << 0U; | ||
870 | } | ||
871 | static inline u32 nvl_intr_tx_replay_v(u32 r) | ||
872 | { | ||
873 | return (r >> 0U) & 0x1U; | ||
874 | } | ||
875 | static inline u32 nvl_intr_tx_recovery_short_f(u32 v) | ||
876 | { | ||
877 | return (v & 0x1U) << 1U; | ||
878 | } | ||
879 | static inline u32 nvl_intr_tx_recovery_short_m(void) | ||
880 | { | ||
881 | return 0x1U << 1U; | ||
882 | } | ||
883 | static inline u32 nvl_intr_tx_recovery_short_v(u32 r) | ||
884 | { | ||
885 | return (r >> 1U) & 0x1U; | ||
886 | } | ||
887 | static inline u32 nvl_intr_tx_recovery_long_f(u32 v) | ||
888 | { | ||
889 | return (v & 0x1U) << 2U; | ||
890 | } | ||
891 | static inline u32 nvl_intr_tx_recovery_long_m(void) | ||
892 | { | ||
893 | return 0x1U << 2U; | ||
894 | } | ||
895 | static inline u32 nvl_intr_tx_recovery_long_v(u32 r) | ||
896 | { | ||
897 | return (r >> 2U) & 0x1U; | ||
898 | } | ||
899 | static inline u32 nvl_intr_tx_fault_ram_f(u32 v) | ||
900 | { | ||
901 | return (v & 0x1U) << 4U; | ||
902 | } | ||
903 | static inline u32 nvl_intr_tx_fault_ram_m(void) | ||
904 | { | ||
905 | return 0x1U << 4U; | ||
906 | } | ||
907 | static inline u32 nvl_intr_tx_fault_ram_v(u32 r) | ||
908 | { | ||
909 | return (r >> 4U) & 0x1U; | ||
910 | } | ||
911 | static inline u32 nvl_intr_tx_fault_interface_f(u32 v) | ||
912 | { | ||
913 | return (v & 0x1U) << 5U; | ||
914 | } | ||
915 | static inline u32 nvl_intr_tx_fault_interface_m(void) | ||
916 | { | ||
917 | return 0x1U << 5U; | ||
918 | } | ||
919 | static inline u32 nvl_intr_tx_fault_interface_v(u32 r) | ||
920 | { | ||
921 | return (r >> 5U) & 0x1U; | ||
922 | } | ||
923 | static inline u32 nvl_intr_tx_fault_sublink_change_f(u32 v) | ||
924 | { | ||
925 | return (v & 0x1U) << 8U; | ||
926 | } | ||
927 | static inline u32 nvl_intr_tx_fault_sublink_change_m(void) | ||
928 | { | ||
929 | return 0x1U << 8U; | ||
930 | } | ||
931 | static inline u32 nvl_intr_tx_fault_sublink_change_v(u32 r) | ||
932 | { | ||
933 | return (r >> 8U) & 0x1U; | ||
934 | } | ||
935 | static inline u32 nvl_intr_rx_fault_sublink_change_f(u32 v) | ||
936 | { | ||
937 | return (v & 0x1U) << 16U; | ||
938 | } | ||
939 | static inline u32 nvl_intr_rx_fault_sublink_change_m(void) | ||
940 | { | ||
941 | return 0x1U << 16U; | ||
942 | } | ||
943 | static inline u32 nvl_intr_rx_fault_sublink_change_v(u32 r) | ||
944 | { | ||
945 | return (r >> 16U) & 0x1U; | ||
946 | } | ||
947 | static inline u32 nvl_intr_rx_fault_dl_protocol_f(u32 v) | ||
948 | { | ||
949 | return (v & 0x1U) << 20U; | ||
950 | } | ||
951 | static inline u32 nvl_intr_rx_fault_dl_protocol_m(void) | ||
952 | { | ||
953 | return 0x1U << 20U; | ||
954 | } | ||
955 | static inline u32 nvl_intr_rx_fault_dl_protocol_v(u32 r) | ||
956 | { | ||
957 | return (r >> 20U) & 0x1U; | ||
958 | } | ||
959 | static inline u32 nvl_intr_rx_short_error_rate_f(u32 v) | ||
960 | { | ||
961 | return (v & 0x1U) << 21U; | ||
962 | } | ||
963 | static inline u32 nvl_intr_rx_short_error_rate_m(void) | ||
964 | { | ||
965 | return 0x1U << 21U; | ||
966 | } | ||
967 | static inline u32 nvl_intr_rx_short_error_rate_v(u32 r) | ||
968 | { | ||
969 | return (r >> 21U) & 0x1U; | ||
970 | } | ||
971 | static inline u32 nvl_intr_rx_long_error_rate_f(u32 v) | ||
972 | { | ||
973 | return (v & 0x1U) << 22U; | ||
974 | } | ||
975 | static inline u32 nvl_intr_rx_long_error_rate_m(void) | ||
976 | { | ||
977 | return 0x1U << 22U; | ||
978 | } | ||
979 | static inline u32 nvl_intr_rx_long_error_rate_v(u32 r) | ||
980 | { | ||
981 | return (r >> 22U) & 0x1U; | ||
982 | } | ||
983 | static inline u32 nvl_intr_rx_ila_trigger_f(u32 v) | ||
984 | { | ||
985 | return (v & 0x1U) << 23U; | ||
986 | } | ||
987 | static inline u32 nvl_intr_rx_ila_trigger_m(void) | ||
988 | { | ||
989 | return 0x1U << 23U; | ||
990 | } | ||
991 | static inline u32 nvl_intr_rx_ila_trigger_v(u32 r) | ||
992 | { | ||
993 | return (r >> 23U) & 0x1U; | ||
994 | } | ||
995 | static inline u32 nvl_intr_rx_crc_counter_f(u32 v) | ||
996 | { | ||
997 | return (v & 0x1U) << 24U; | ||
998 | } | ||
999 | static inline u32 nvl_intr_rx_crc_counter_m(void) | ||
1000 | { | ||
1001 | return 0x1U << 24U; | ||
1002 | } | ||
1003 | static inline u32 nvl_intr_rx_crc_counter_v(u32 r) | ||
1004 | { | ||
1005 | return (r >> 24U) & 0x1U; | ||
1006 | } | ||
1007 | static inline u32 nvl_intr_ltssm_fault_f(u32 v) | ||
1008 | { | ||
1009 | return (v & 0x1U) << 28U; | ||
1010 | } | ||
1011 | static inline u32 nvl_intr_ltssm_fault_m(void) | ||
1012 | { | ||
1013 | return 0x1U << 28U; | ||
1014 | } | ||
1015 | static inline u32 nvl_intr_ltssm_fault_v(u32 r) | ||
1016 | { | ||
1017 | return (r >> 28U) & 0x1U; | ||
1018 | } | ||
1019 | static inline u32 nvl_intr_ltssm_protocol_f(u32 v) | ||
1020 | { | ||
1021 | return (v & 0x1U) << 29U; | ||
1022 | } | ||
1023 | static inline u32 nvl_intr_ltssm_protocol_m(void) | ||
1024 | { | ||
1025 | return 0x1U << 29U; | ||
1026 | } | ||
1027 | static inline u32 nvl_intr_ltssm_protocol_v(u32 r) | ||
1028 | { | ||
1029 | return (r >> 29U) & 0x1U; | ||
1030 | } | ||
1031 | static inline u32 nvl_intr_minion_request_f(u32 v) | ||
1032 | { | ||
1033 | return (v & 0x1U) << 30U; | ||
1034 | } | ||
1035 | static inline u32 nvl_intr_minion_request_m(void) | ||
1036 | { | ||
1037 | return 0x1U << 30U; | ||
1038 | } | ||
1039 | static inline u32 nvl_intr_minion_request_v(u32 r) | ||
1040 | { | ||
1041 | return (r >> 30U) & 0x1U; | ||
1042 | } | ||
1043 | static inline u32 nvl_intr_sw2_r(void) | ||
1044 | { | ||
1045 | return 0x00000054U; | ||
1046 | } | ||
1047 | static inline u32 nvl_intr_minion_r(void) | ||
1048 | { | ||
1049 | return 0x00000060U; | ||
1050 | } | ||
1051 | static inline u32 nvl_intr_minion_tx_replay_f(u32 v) | ||
1052 | { | ||
1053 | return (v & 0x1U) << 0U; | ||
1054 | } | ||
1055 | static inline u32 nvl_intr_minion_tx_replay_m(void) | ||
1056 | { | ||
1057 | return 0x1U << 0U; | ||
1058 | } | ||
1059 | static inline u32 nvl_intr_minion_tx_replay_v(u32 r) | ||
1060 | { | ||
1061 | return (r >> 0U) & 0x1U; | ||
1062 | } | ||
1063 | static inline u32 nvl_intr_minion_tx_recovery_short_f(u32 v) | ||
1064 | { | ||
1065 | return (v & 0x1U) << 1U; | ||
1066 | } | ||
1067 | static inline u32 nvl_intr_minion_tx_recovery_short_m(void) | ||
1068 | { | ||
1069 | return 0x1U << 1U; | ||
1070 | } | ||
1071 | static inline u32 nvl_intr_minion_tx_recovery_short_v(u32 r) | ||
1072 | { | ||
1073 | return (r >> 1U) & 0x1U; | ||
1074 | } | ||
1075 | static inline u32 nvl_intr_minion_tx_recovery_long_f(u32 v) | ||
1076 | { | ||
1077 | return (v & 0x1U) << 2U; | ||
1078 | } | ||
1079 | static inline u32 nvl_intr_minion_tx_recovery_long_m(void) | ||
1080 | { | ||
1081 | return 0x1U << 2U; | ||
1082 | } | ||
1083 | static inline u32 nvl_intr_minion_tx_recovery_long_v(u32 r) | ||
1084 | { | ||
1085 | return (r >> 2U) & 0x1U; | ||
1086 | } | ||
1087 | static inline u32 nvl_intr_minion_tx_fault_ram_f(u32 v) | ||
1088 | { | ||
1089 | return (v & 0x1U) << 4U; | ||
1090 | } | ||
1091 | static inline u32 nvl_intr_minion_tx_fault_ram_m(void) | ||
1092 | { | ||
1093 | return 0x1U << 4U; | ||
1094 | } | ||
1095 | static inline u32 nvl_intr_minion_tx_fault_ram_v(u32 r) | ||
1096 | { | ||
1097 | return (r >> 4U) & 0x1U; | ||
1098 | } | ||
1099 | static inline u32 nvl_intr_minion_tx_fault_interface_f(u32 v) | ||
1100 | { | ||
1101 | return (v & 0x1U) << 5U; | ||
1102 | } | ||
1103 | static inline u32 nvl_intr_minion_tx_fault_interface_m(void) | ||
1104 | { | ||
1105 | return 0x1U << 5U; | ||
1106 | } | ||
1107 | static inline u32 nvl_intr_minion_tx_fault_interface_v(u32 r) | ||
1108 | { | ||
1109 | return (r >> 5U) & 0x1U; | ||
1110 | } | ||
1111 | static inline u32 nvl_intr_minion_tx_fault_sublink_change_f(u32 v) | ||
1112 | { | ||
1113 | return (v & 0x1U) << 8U; | ||
1114 | } | ||
1115 | static inline u32 nvl_intr_minion_tx_fault_sublink_change_m(void) | ||
1116 | { | ||
1117 | return 0x1U << 8U; | ||
1118 | } | ||
1119 | static inline u32 nvl_intr_minion_tx_fault_sublink_change_v(u32 r) | ||
1120 | { | ||
1121 | return (r >> 8U) & 0x1U; | ||
1122 | } | ||
1123 | static inline u32 nvl_intr_minion_rx_fault_sublink_change_f(u32 v) | ||
1124 | { | ||
1125 | return (v & 0x1U) << 16U; | ||
1126 | } | ||
1127 | static inline u32 nvl_intr_minion_rx_fault_sublink_change_m(void) | ||
1128 | { | ||
1129 | return 0x1U << 16U; | ||
1130 | } | ||
1131 | static inline u32 nvl_intr_minion_rx_fault_sublink_change_v(u32 r) | ||
1132 | { | ||
1133 | return (r >> 16U) & 0x1U; | ||
1134 | } | ||
1135 | static inline u32 nvl_intr_minion_rx_fault_dl_protocol_f(u32 v) | ||
1136 | { | ||
1137 | return (v & 0x1U) << 20U; | ||
1138 | } | ||
1139 | static inline u32 nvl_intr_minion_rx_fault_dl_protocol_m(void) | ||
1140 | { | ||
1141 | return 0x1U << 20U; | ||
1142 | } | ||
1143 | static inline u32 nvl_intr_minion_rx_fault_dl_protocol_v(u32 r) | ||
1144 | { | ||
1145 | return (r >> 20U) & 0x1U; | ||
1146 | } | ||
1147 | static inline u32 nvl_intr_minion_rx_short_error_rate_f(u32 v) | ||
1148 | { | ||
1149 | return (v & 0x1U) << 21U; | ||
1150 | } | ||
1151 | static inline u32 nvl_intr_minion_rx_short_error_rate_m(void) | ||
1152 | { | ||
1153 | return 0x1U << 21U; | ||
1154 | } | ||
1155 | static inline u32 nvl_intr_minion_rx_short_error_rate_v(u32 r) | ||
1156 | { | ||
1157 | return (r >> 21U) & 0x1U; | ||
1158 | } | ||
1159 | static inline u32 nvl_intr_minion_rx_long_error_rate_f(u32 v) | ||
1160 | { | ||
1161 | return (v & 0x1U) << 22U; | ||
1162 | } | ||
1163 | static inline u32 nvl_intr_minion_rx_long_error_rate_m(void) | ||
1164 | { | ||
1165 | return 0x1U << 22U; | ||
1166 | } | ||
1167 | static inline u32 nvl_intr_minion_rx_long_error_rate_v(u32 r) | ||
1168 | { | ||
1169 | return (r >> 22U) & 0x1U; | ||
1170 | } | ||
1171 | static inline u32 nvl_intr_minion_rx_ila_trigger_f(u32 v) | ||
1172 | { | ||
1173 | return (v & 0x1U) << 23U; | ||
1174 | } | ||
1175 | static inline u32 nvl_intr_minion_rx_ila_trigger_m(void) | ||
1176 | { | ||
1177 | return 0x1U << 23U; | ||
1178 | } | ||
1179 | static inline u32 nvl_intr_minion_rx_ila_trigger_v(u32 r) | ||
1180 | { | ||
1181 | return (r >> 23U) & 0x1U; | ||
1182 | } | ||
1183 | static inline u32 nvl_intr_minion_rx_crc_counter_f(u32 v) | ||
1184 | { | ||
1185 | return (v & 0x1U) << 24U; | ||
1186 | } | ||
1187 | static inline u32 nvl_intr_minion_rx_crc_counter_m(void) | ||
1188 | { | ||
1189 | return 0x1U << 24U; | ||
1190 | } | ||
1191 | static inline u32 nvl_intr_minion_rx_crc_counter_v(u32 r) | ||
1192 | { | ||
1193 | return (r >> 24U) & 0x1U; | ||
1194 | } | ||
1195 | static inline u32 nvl_intr_minion_ltssm_fault_f(u32 v) | ||
1196 | { | ||
1197 | return (v & 0x1U) << 28U; | ||
1198 | } | ||
1199 | static inline u32 nvl_intr_minion_ltssm_fault_m(void) | ||
1200 | { | ||
1201 | return 0x1U << 28U; | ||
1202 | } | ||
1203 | static inline u32 nvl_intr_minion_ltssm_fault_v(u32 r) | ||
1204 | { | ||
1205 | return (r >> 28U) & 0x1U; | ||
1206 | } | ||
1207 | static inline u32 nvl_intr_minion_ltssm_protocol_f(u32 v) | ||
1208 | { | ||
1209 | return (v & 0x1U) << 29U; | ||
1210 | } | ||
1211 | static inline u32 nvl_intr_minion_ltssm_protocol_m(void) | ||
1212 | { | ||
1213 | return 0x1U << 29U; | ||
1214 | } | ||
1215 | static inline u32 nvl_intr_minion_ltssm_protocol_v(u32 r) | ||
1216 | { | ||
1217 | return (r >> 29U) & 0x1U; | ||
1218 | } | ||
1219 | static inline u32 nvl_intr_minion_minion_request_f(u32 v) | ||
1220 | { | ||
1221 | return (v & 0x1U) << 30U; | ||
1222 | } | ||
1223 | static inline u32 nvl_intr_minion_minion_request_m(void) | ||
1224 | { | ||
1225 | return 0x1U << 30U; | ||
1226 | } | ||
1227 | static inline u32 nvl_intr_minion_minion_request_v(u32 r) | ||
1228 | { | ||
1229 | return (r >> 30U) & 0x1U; | ||
1230 | } | ||
1231 | static inline u32 nvl_intr_nonstall_en_r(void) | ||
1232 | { | ||
1233 | return 0x0000005cU; | ||
1234 | } | ||
1235 | static inline u32 nvl_intr_stall_en_r(void) | ||
1236 | { | ||
1237 | return 0x00000058U; | ||
1238 | } | ||
1239 | static inline u32 nvl_intr_stall_en_tx_replay_f(u32 v) | ||
1240 | { | ||
1241 | return (v & 0x1U) << 0U; | ||
1242 | } | ||
1243 | static inline u32 nvl_intr_stall_en_tx_replay_m(void) | ||
1244 | { | ||
1245 | return 0x1U << 0U; | ||
1246 | } | ||
1247 | static inline u32 nvl_intr_stall_en_tx_replay_v(u32 r) | ||
1248 | { | ||
1249 | return (r >> 0U) & 0x1U; | ||
1250 | } | ||
1251 | static inline u32 nvl_intr_stall_en_tx_recovery_short_f(u32 v) | ||
1252 | { | ||
1253 | return (v & 0x1U) << 1U; | ||
1254 | } | ||
1255 | static inline u32 nvl_intr_stall_en_tx_recovery_short_m(void) | ||
1256 | { | ||
1257 | return 0x1U << 1U; | ||
1258 | } | ||
1259 | static inline u32 nvl_intr_stall_en_tx_recovery_short_v(u32 r) | ||
1260 | { | ||
1261 | return (r >> 1U) & 0x1U; | ||
1262 | } | ||
1263 | static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_v(void) | ||
1264 | { | ||
1265 | return 0x00000001U; | ||
1266 | } | ||
1267 | static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_f(void) | ||
1268 | { | ||
1269 | return 0x2U; | ||
1270 | } | ||
1271 | static inline u32 nvl_intr_stall_en_tx_recovery_long_f(u32 v) | ||
1272 | { | ||
1273 | return (v & 0x1U) << 2U; | ||
1274 | } | ||
1275 | static inline u32 nvl_intr_stall_en_tx_recovery_long_m(void) | ||
1276 | { | ||
1277 | return 0x1U << 2U; | ||
1278 | } | ||
1279 | static inline u32 nvl_intr_stall_en_tx_recovery_long_v(u32 r) | ||
1280 | { | ||
1281 | return (r >> 2U) & 0x1U; | ||
1282 | } | ||
1283 | static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_v(void) | ||
1284 | { | ||
1285 | return 0x00000001U; | ||
1286 | } | ||
1287 | static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_f(void) | ||
1288 | { | ||
1289 | return 0x4U; | ||
1290 | } | ||
1291 | static inline u32 nvl_intr_stall_en_tx_fault_ram_f(u32 v) | ||
1292 | { | ||
1293 | return (v & 0x1U) << 4U; | ||
1294 | } | ||
1295 | static inline u32 nvl_intr_stall_en_tx_fault_ram_m(void) | ||
1296 | { | ||
1297 | return 0x1U << 4U; | ||
1298 | } | ||
1299 | static inline u32 nvl_intr_stall_en_tx_fault_ram_v(u32 r) | ||
1300 | { | ||
1301 | return (r >> 4U) & 0x1U; | ||
1302 | } | ||
1303 | static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_v(void) | ||
1304 | { | ||
1305 | return 0x00000001U; | ||
1306 | } | ||
1307 | static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_f(void) | ||
1308 | { | ||
1309 | return 0x10U; | ||
1310 | } | ||
1311 | static inline u32 nvl_intr_stall_en_tx_fault_interface_f(u32 v) | ||
1312 | { | ||
1313 | return (v & 0x1U) << 5U; | ||
1314 | } | ||
1315 | static inline u32 nvl_intr_stall_en_tx_fault_interface_m(void) | ||
1316 | { | ||
1317 | return 0x1U << 5U; | ||
1318 | } | ||
1319 | static inline u32 nvl_intr_stall_en_tx_fault_interface_v(u32 r) | ||
1320 | { | ||
1321 | return (r >> 5U) & 0x1U; | ||
1322 | } | ||
1323 | static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_v(void) | ||
1324 | { | ||
1325 | return 0x00000001U; | ||
1326 | } | ||
1327 | static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_f(void) | ||
1328 | { | ||
1329 | return 0x20U; | ||
1330 | } | ||
1331 | static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_f(u32 v) | ||
1332 | { | ||
1333 | return (v & 0x1U) << 8U; | ||
1334 | } | ||
1335 | static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_m(void) | ||
1336 | { | ||
1337 | return 0x1U << 8U; | ||
1338 | } | ||
1339 | static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_v(u32 r) | ||
1340 | { | ||
1341 | return (r >> 8U) & 0x1U; | ||
1342 | } | ||
1343 | static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_v(void) | ||
1344 | { | ||
1345 | return 0x00000001U; | ||
1346 | } | ||
1347 | static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_f(void) | ||
1348 | { | ||
1349 | return 0x100U; | ||
1350 | } | ||
1351 | static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_f(u32 v) | ||
1352 | { | ||
1353 | return (v & 0x1U) << 16U; | ||
1354 | } | ||
1355 | static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_m(void) | ||
1356 | { | ||
1357 | return 0x1U << 16U; | ||
1358 | } | ||
1359 | static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_v(u32 r) | ||
1360 | { | ||
1361 | return (r >> 16U) & 0x1U; | ||
1362 | } | ||
1363 | static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_v(void) | ||
1364 | { | ||
1365 | return 0x00000001U; | ||
1366 | } | ||
1367 | static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_f(void) | ||
1368 | { | ||
1369 | return 0x10000U; | ||
1370 | } | ||
1371 | static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_f(u32 v) | ||
1372 | { | ||
1373 | return (v & 0x1U) << 20U; | ||
1374 | } | ||
1375 | static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_m(void) | ||
1376 | { | ||
1377 | return 0x1U << 20U; | ||
1378 | } | ||
1379 | static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_v(u32 r) | ||
1380 | { | ||
1381 | return (r >> 20U) & 0x1U; | ||
1382 | } | ||
1383 | static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_v(void) | ||
1384 | { | ||
1385 | return 0x00000001U; | ||
1386 | } | ||
1387 | static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_f(void) | ||
1388 | { | ||
1389 | return 0x100000U; | ||
1390 | } | ||
1391 | static inline u32 nvl_intr_stall_en_rx_short_error_rate_f(u32 v) | ||
1392 | { | ||
1393 | return (v & 0x1U) << 21U; | ||
1394 | } | ||
1395 | static inline u32 nvl_intr_stall_en_rx_short_error_rate_m(void) | ||
1396 | { | ||
1397 | return 0x1U << 21U; | ||
1398 | } | ||
1399 | static inline u32 nvl_intr_stall_en_rx_short_error_rate_v(u32 r) | ||
1400 | { | ||
1401 | return (r >> 21U) & 0x1U; | ||
1402 | } | ||
1403 | static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_v(void) | ||
1404 | { | ||
1405 | return 0x00000001U; | ||
1406 | } | ||
1407 | static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_f(void) | ||
1408 | { | ||
1409 | return 0x200000U; | ||
1410 | } | ||
1411 | static inline u32 nvl_intr_stall_en_rx_long_error_rate_f(u32 v) | ||
1412 | { | ||
1413 | return (v & 0x1U) << 22U; | ||
1414 | } | ||
1415 | static inline u32 nvl_intr_stall_en_rx_long_error_rate_m(void) | ||
1416 | { | ||
1417 | return 0x1U << 22U; | ||
1418 | } | ||
1419 | static inline u32 nvl_intr_stall_en_rx_long_error_rate_v(u32 r) | ||
1420 | { | ||
1421 | return (r >> 22U) & 0x1U; | ||
1422 | } | ||
1423 | static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_v(void) | ||
1424 | { | ||
1425 | return 0x00000001U; | ||
1426 | } | ||
1427 | static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_f(void) | ||
1428 | { | ||
1429 | return 0x400000U; | ||
1430 | } | ||
1431 | static inline u32 nvl_intr_stall_en_rx_ila_trigger_f(u32 v) | ||
1432 | { | ||
1433 | return (v & 0x1U) << 23U; | ||
1434 | } | ||
1435 | static inline u32 nvl_intr_stall_en_rx_ila_trigger_m(void) | ||
1436 | { | ||
1437 | return 0x1U << 23U; | ||
1438 | } | ||
1439 | static inline u32 nvl_intr_stall_en_rx_ila_trigger_v(u32 r) | ||
1440 | { | ||
1441 | return (r >> 23U) & 0x1U; | ||
1442 | } | ||
1443 | static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_v(void) | ||
1444 | { | ||
1445 | return 0x00000001U; | ||
1446 | } | ||
1447 | static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_f(void) | ||
1448 | { | ||
1449 | return 0x800000U; | ||
1450 | } | ||
1451 | static inline u32 nvl_intr_stall_en_rx_crc_counter_f(u32 v) | ||
1452 | { | ||
1453 | return (v & 0x1U) << 24U; | ||
1454 | } | ||
1455 | static inline u32 nvl_intr_stall_en_rx_crc_counter_m(void) | ||
1456 | { | ||
1457 | return 0x1U << 24U; | ||
1458 | } | ||
1459 | static inline u32 nvl_intr_stall_en_rx_crc_counter_v(u32 r) | ||
1460 | { | ||
1461 | return (r >> 24U) & 0x1U; | ||
1462 | } | ||
1463 | static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_v(void) | ||
1464 | { | ||
1465 | return 0x00000001U; | ||
1466 | } | ||
1467 | static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_f(void) | ||
1468 | { | ||
1469 | return 0x1000000U; | ||
1470 | } | ||
1471 | static inline u32 nvl_intr_stall_en_ltssm_fault_f(u32 v) | ||
1472 | { | ||
1473 | return (v & 0x1U) << 28U; | ||
1474 | } | ||
1475 | static inline u32 nvl_intr_stall_en_ltssm_fault_m(void) | ||
1476 | { | ||
1477 | return 0x1U << 28U; | ||
1478 | } | ||
1479 | static inline u32 nvl_intr_stall_en_ltssm_fault_v(u32 r) | ||
1480 | { | ||
1481 | return (r >> 28U) & 0x1U; | ||
1482 | } | ||
1483 | static inline u32 nvl_intr_stall_en_ltssm_fault_enable_v(void) | ||
1484 | { | ||
1485 | return 0x00000001U; | ||
1486 | } | ||
1487 | static inline u32 nvl_intr_stall_en_ltssm_fault_enable_f(void) | ||
1488 | { | ||
1489 | return 0x10000000U; | ||
1490 | } | ||
1491 | static inline u32 nvl_intr_stall_en_ltssm_protocol_f(u32 v) | ||
1492 | { | ||
1493 | return (v & 0x1U) << 29U; | ||
1494 | } | ||
1495 | static inline u32 nvl_intr_stall_en_ltssm_protocol_m(void) | ||
1496 | { | ||
1497 | return 0x1U << 29U; | ||
1498 | } | ||
1499 | static inline u32 nvl_intr_stall_en_ltssm_protocol_v(u32 r) | ||
1500 | { | ||
1501 | return (r >> 29U) & 0x1U; | ||
1502 | } | ||
1503 | static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_v(void) | ||
1504 | { | ||
1505 | return 0x00000001U; | ||
1506 | } | ||
1507 | static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_f(void) | ||
1508 | { | ||
1509 | return 0x20000000U; | ||
1510 | } | ||
1511 | static inline u32 nvl_intr_stall_en_minion_request_f(u32 v) | ||
1512 | { | ||
1513 | return (v & 0x1U) << 30U; | ||
1514 | } | ||
1515 | static inline u32 nvl_intr_stall_en_minion_request_m(void) | ||
1516 | { | ||
1517 | return 0x1U << 30U; | ||
1518 | } | ||
1519 | static inline u32 nvl_intr_stall_en_minion_request_v(u32 r) | ||
1520 | { | ||
1521 | return (r >> 30U) & 0x1U; | ||
1522 | } | ||
1523 | static inline u32 nvl_intr_stall_en_minion_request_enable_v(void) | ||
1524 | { | ||
1525 | return 0x00000001U; | ||
1526 | } | ||
1527 | static inline u32 nvl_intr_stall_en_minion_request_enable_f(void) | ||
1528 | { | ||
1529 | return 0x40000000U; | ||
1530 | } | ||
1531 | static inline u32 nvl_br0_cfg_cal_r(void) | ||
1532 | { | ||
1533 | return 0x0000281cU; | ||
1534 | } | ||
1535 | static inline u32 nvl_br0_cfg_cal_rxcal_f(u32 v) | ||
1536 | { | ||
1537 | return (v & 0x1U) << 0U; | ||
1538 | } | ||
1539 | static inline u32 nvl_br0_cfg_cal_rxcal_m(void) | ||
1540 | { | ||
1541 | return 0x1U << 0U; | ||
1542 | } | ||
1543 | static inline u32 nvl_br0_cfg_cal_rxcal_v(u32 r) | ||
1544 | { | ||
1545 | return (r >> 0U) & 0x1U; | ||
1546 | } | ||
1547 | static inline u32 nvl_br0_cfg_cal_rxcal_on_v(void) | ||
1548 | { | ||
1549 | return 0x00000001U; | ||
1550 | } | ||
1551 | static inline u32 nvl_br0_cfg_cal_rxcal_on_f(void) | ||
1552 | { | ||
1553 | return 0x1U; | ||
1554 | } | ||
1555 | static inline u32 nvl_br0_cfg_status_cal_r(void) | ||
1556 | { | ||
1557 | return 0x00002838U; | ||
1558 | } | ||
1559 | static inline u32 nvl_br0_cfg_status_cal_rxcal_done_f(u32 v) | ||
1560 | { | ||
1561 | return (v & 0x1U) << 2U; | ||
1562 | } | ||
1563 | static inline u32 nvl_br0_cfg_status_cal_rxcal_done_m(void) | ||
1564 | { | ||
1565 | return 0x1U << 2U; | ||
1566 | } | ||
1567 | static inline u32 nvl_br0_cfg_status_cal_rxcal_done_v(u32 r) | ||
1568 | { | ||
1569 | return (r >> 2U) & 0x1U; | ||
1570 | } | ||
1571 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h new file mode 100644 index 00000000..9d33a9fd --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h | |||
@@ -0,0 +1,311 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_nvlinkip_discovery_gv100_h_ | ||
57 | #define _hw_nvlinkip_discovery_gv100_h_ | ||
58 | |||
59 | static inline u32 nvlinkip_discovery_common_r(void) | ||
60 | { | ||
61 | return 0x00000000U; | ||
62 | } | ||
63 | static inline u32 nvlinkip_discovery_common_entry_f(u32 v) | ||
64 | { | ||
65 | return (v & 0x3U) << 0U; | ||
66 | } | ||
67 | static inline u32 nvlinkip_discovery_common_entry_v(u32 r) | ||
68 | { | ||
69 | return (r >> 0U) & 0x3U; | ||
70 | } | ||
71 | static inline u32 nvlinkip_discovery_common_entry_invalid_v(void) | ||
72 | { | ||
73 | return 0x00000000U; | ||
74 | } | ||
75 | static inline u32 nvlinkip_discovery_common_entry_enum_v(void) | ||
76 | { | ||
77 | return 0x00000001U; | ||
78 | } | ||
79 | static inline u32 nvlinkip_discovery_common_entry_data1_v(void) | ||
80 | { | ||
81 | return 0x00000002U; | ||
82 | } | ||
83 | static inline u32 nvlinkip_discovery_common_entry_data2_v(void) | ||
84 | { | ||
85 | return 0x00000003U; | ||
86 | } | ||
87 | static inline u32 nvlinkip_discovery_common_contents_f(u32 v) | ||
88 | { | ||
89 | return (v & 0x1fffffffU) << 2U; | ||
90 | } | ||
91 | static inline u32 nvlinkip_discovery_common_contents_v(u32 r) | ||
92 | { | ||
93 | return (r >> 2U) & 0x1fffffffU; | ||
94 | } | ||
95 | static inline u32 nvlinkip_discovery_common_chain_f(u32 v) | ||
96 | { | ||
97 | return (v & 0x1U) << 31U; | ||
98 | } | ||
99 | static inline u32 nvlinkip_discovery_common_chain_v(u32 r) | ||
100 | { | ||
101 | return (r >> 31U) & 0x1U; | ||
102 | } | ||
103 | static inline u32 nvlinkip_discovery_common_chain_enable_v(void) | ||
104 | { | ||
105 | return 0x00000001U; | ||
106 | } | ||
107 | static inline u32 nvlinkip_discovery_common_device_f(u32 v) | ||
108 | { | ||
109 | return (v & 0x3fU) << 2U; | ||
110 | } | ||
111 | static inline u32 nvlinkip_discovery_common_device_v(u32 r) | ||
112 | { | ||
113 | return (r >> 2U) & 0x3fU; | ||
114 | } | ||
115 | static inline u32 nvlinkip_discovery_common_device_invalid_v(void) | ||
116 | { | ||
117 | return 0x00000000U; | ||
118 | } | ||
119 | static inline u32 nvlinkip_discovery_common_device_ioctrl_v(void) | ||
120 | { | ||
121 | return 0x00000001U; | ||
122 | } | ||
123 | static inline u32 nvlinkip_discovery_common_device_nvltl_v(void) | ||
124 | { | ||
125 | return 0x00000002U; | ||
126 | } | ||
127 | static inline u32 nvlinkip_discovery_common_device_nvlink_v(void) | ||
128 | { | ||
129 | return 0x00000003U; | ||
130 | } | ||
131 | static inline u32 nvlinkip_discovery_common_device_minion_v(void) | ||
132 | { | ||
133 | return 0x00000004U; | ||
134 | } | ||
135 | static inline u32 nvlinkip_discovery_common_device_nvlipt_v(void) | ||
136 | { | ||
137 | return 0x00000005U; | ||
138 | } | ||
139 | static inline u32 nvlinkip_discovery_common_device_nvltlc_v(void) | ||
140 | { | ||
141 | return 0x00000006U; | ||
142 | } | ||
143 | static inline u32 nvlinkip_discovery_common_device_dlpl_v(void) | ||
144 | { | ||
145 | return 0x0000000bU; | ||
146 | } | ||
147 | static inline u32 nvlinkip_discovery_common_device_ioctrlmif_v(void) | ||
148 | { | ||
149 | return 0x00000007U; | ||
150 | } | ||
151 | static inline u32 nvlinkip_discovery_common_device_dlpl_multicast_v(void) | ||
152 | { | ||
153 | return 0x00000008U; | ||
154 | } | ||
155 | static inline u32 nvlinkip_discovery_common_device_nvltlc_multicast_v(void) | ||
156 | { | ||
157 | return 0x00000009U; | ||
158 | } | ||
159 | static inline u32 nvlinkip_discovery_common_device_ioctrlmif_multicast_v(void) | ||
160 | { | ||
161 | return 0x0000000aU; | ||
162 | } | ||
163 | static inline u32 nvlinkip_discovery_common_device_sioctrl_v(void) | ||
164 | { | ||
165 | return 0x0000000cU; | ||
166 | } | ||
167 | static inline u32 nvlinkip_discovery_common_device_tioctrl_v(void) | ||
168 | { | ||
169 | return 0x0000000dU; | ||
170 | } | ||
171 | static inline u32 nvlinkip_discovery_common_id_f(u32 v) | ||
172 | { | ||
173 | return (v & 0xffU) << 8U; | ||
174 | } | ||
175 | static inline u32 nvlinkip_discovery_common_id_v(u32 r) | ||
176 | { | ||
177 | return (r >> 8U) & 0xffU; | ||
178 | } | ||
179 | static inline u32 nvlinkip_discovery_common_version_f(u32 v) | ||
180 | { | ||
181 | return (v & 0x7ffU) << 20U; | ||
182 | } | ||
183 | static inline u32 nvlinkip_discovery_common_version_v(u32 r) | ||
184 | { | ||
185 | return (r >> 20U) & 0x7ffU; | ||
186 | } | ||
187 | static inline u32 nvlinkip_discovery_common_pri_base_f(u32 v) | ||
188 | { | ||
189 | return (v & 0xfffU) << 12U; | ||
190 | } | ||
191 | static inline u32 nvlinkip_discovery_common_pri_base_v(u32 r) | ||
192 | { | ||
193 | return (r >> 12U) & 0xfffU; | ||
194 | } | ||
195 | static inline u32 nvlinkip_discovery_common_intr_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x1fU) << 7U; | ||
198 | } | ||
199 | static inline u32 nvlinkip_discovery_common_intr_v(u32 r) | ||
200 | { | ||
201 | return (r >> 7U) & 0x1fU; | ||
202 | } | ||
203 | static inline u32 nvlinkip_discovery_common_reset_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x1fU) << 2U; | ||
206 | } | ||
207 | static inline u32 nvlinkip_discovery_common_reset_v(u32 r) | ||
208 | { | ||
209 | return (r >> 2U) & 0x1fU; | ||
210 | } | ||
211 | static inline u32 nvlinkip_discovery_common_ioctrl_length_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x3fU) << 24U; | ||
214 | } | ||
215 | static inline u32 nvlinkip_discovery_common_ioctrl_length_v(u32 r) | ||
216 | { | ||
217 | return (r >> 24U) & 0x3fU; | ||
218 | } | ||
219 | static inline u32 nvlinkip_discovery_common_dlpl_num_tx_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x7U) << 24U; | ||
222 | } | ||
223 | static inline u32 nvlinkip_discovery_common_dlpl_num_tx_v(u32 r) | ||
224 | { | ||
225 | return (r >> 24U) & 0x7U; | ||
226 | } | ||
227 | static inline u32 nvlinkip_discovery_common_dlpl_num_rx_f(u32 v) | ||
228 | { | ||
229 | return (v & 0x7U) << 27U; | ||
230 | } | ||
231 | static inline u32 nvlinkip_discovery_common_dlpl_num_rx_v(u32 r) | ||
232 | { | ||
233 | return (r >> 27U) & 0x7U; | ||
234 | } | ||
235 | static inline u32 nvlinkip_discovery_common_data1_ioctrl_length_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x7ffffU) << 12U; | ||
238 | } | ||
239 | static inline u32 nvlinkip_discovery_common_data1_ioctrl_length_v(u32 r) | ||
240 | { | ||
241 | return (r >> 12U) & 0x7ffffU; | ||
242 | } | ||
243 | static inline u32 nvlinkip_discovery_common_data2_type_f(u32 v) | ||
244 | { | ||
245 | return (v & 0x1fU) << 26U; | ||
246 | } | ||
247 | static inline u32 nvlinkip_discovery_common_data2_type_v(u32 r) | ||
248 | { | ||
249 | return (r >> 26U) & 0x1fU; | ||
250 | } | ||
251 | static inline u32 nvlinkip_discovery_common_data2_type_invalid_v(void) | ||
252 | { | ||
253 | return 0x00000000U; | ||
254 | } | ||
255 | static inline u32 nvlinkip_discovery_common_data2_type_pllcontrol_v(void) | ||
256 | { | ||
257 | return 0x00000001U; | ||
258 | } | ||
259 | static inline u32 nvlinkip_discovery_common_data2_type_resetreg_v(void) | ||
260 | { | ||
261 | return 0x00000002U; | ||
262 | } | ||
263 | static inline u32 nvlinkip_discovery_common_data2_type_intrreg_v(void) | ||
264 | { | ||
265 | return 0x00000003U; | ||
266 | } | ||
267 | static inline u32 nvlinkip_discovery_common_data2_type_discovery_v(void) | ||
268 | { | ||
269 | return 0x00000004U; | ||
270 | } | ||
271 | static inline u32 nvlinkip_discovery_common_data2_type_unicast_v(void) | ||
272 | { | ||
273 | return 0x00000005U; | ||
274 | } | ||
275 | static inline u32 nvlinkip_discovery_common_data2_type_broadcast_v(void) | ||
276 | { | ||
277 | return 0x00000006U; | ||
278 | } | ||
279 | static inline u32 nvlinkip_discovery_common_data2_addr_f(u32 v) | ||
280 | { | ||
281 | return (v & 0xffffffU) << 2U; | ||
282 | } | ||
283 | static inline u32 nvlinkip_discovery_common_data2_addr_v(u32 r) | ||
284 | { | ||
285 | return (r >> 2U) & 0xffffffU; | ||
286 | } | ||
287 | static inline u32 nvlinkip_discovery_common_dlpl_data2_type_f(u32 v) | ||
288 | { | ||
289 | return (v & 0x1fU) << 26U; | ||
290 | } | ||
291 | static inline u32 nvlinkip_discovery_common_dlpl_data2_type_v(u32 r) | ||
292 | { | ||
293 | return (r >> 26U) & 0x1fU; | ||
294 | } | ||
295 | static inline u32 nvlinkip_discovery_common_dlpl_data2_master_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x1U) << 15U; | ||
298 | } | ||
299 | static inline u32 nvlinkip_discovery_common_dlpl_data2_master_v(u32 r) | ||
300 | { | ||
301 | return (r >> 15U) & 0x1U; | ||
302 | } | ||
303 | static inline u32 nvlinkip_discovery_common_dlpl_data2_masterid_f(u32 v) | ||
304 | { | ||
305 | return (v & 0x7fU) << 8U; | ||
306 | } | ||
307 | static inline u32 nvlinkip_discovery_common_dlpl_data2_masterid_v(u32 r) | ||
308 | { | ||
309 | return (r >> 8U) & 0x7fU; | ||
310 | } | ||
311 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h new file mode 100644 index 00000000..5f73fabd --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h | |||
@@ -0,0 +1,279 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_nvlipt_gv100_h_ | ||
57 | #define _hw_nvlipt_gv100_h_ | ||
58 | |||
59 | static inline u32 nvlipt_intr_control_link0_r(void) | ||
60 | { | ||
61 | return 0x000004b4U; | ||
62 | } | ||
63 | static inline u32 nvlipt_intr_control_link0_stallenable_f(u32 v) | ||
64 | { | ||
65 | return (v & 0x1U) << 0U; | ||
66 | } | ||
67 | static inline u32 nvlipt_intr_control_link0_stallenable_m(void) | ||
68 | { | ||
69 | return 0x1U << 0U; | ||
70 | } | ||
71 | static inline u32 nvlipt_intr_control_link0_stallenable_v(u32 r) | ||
72 | { | ||
73 | return (r >> 0U) & 0x1U; | ||
74 | } | ||
75 | static inline u32 nvlipt_intr_control_link0_nostallenable_f(u32 v) | ||
76 | { | ||
77 | return (v & 0x1U) << 1U; | ||
78 | } | ||
79 | static inline u32 nvlipt_intr_control_link0_nostallenable_m(void) | ||
80 | { | ||
81 | return 0x1U << 1U; | ||
82 | } | ||
83 | static inline u32 nvlipt_intr_control_link0_nostallenable_v(u32 r) | ||
84 | { | ||
85 | return (r >> 1U) & 0x1U; | ||
86 | } | ||
87 | static inline u32 nvlipt_err_uc_status_link0_r(void) | ||
88 | { | ||
89 | return 0x00000524U; | ||
90 | } | ||
91 | static inline u32 nvlipt_err_uc_status_link0_dlprotocol_f(u32 v) | ||
92 | { | ||
93 | return (v & 0x1U) << 4U; | ||
94 | } | ||
95 | static inline u32 nvlipt_err_uc_status_link0_dlprotocol_v(u32 r) | ||
96 | { | ||
97 | return (r >> 4U) & 0x1U; | ||
98 | } | ||
99 | static inline u32 nvlipt_err_uc_status_link0_datapoisoned_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1U) << 12U; | ||
102 | } | ||
103 | static inline u32 nvlipt_err_uc_status_link0_datapoisoned_v(u32 r) | ||
104 | { | ||
105 | return (r >> 12U) & 0x1U; | ||
106 | } | ||
107 | static inline u32 nvlipt_err_uc_status_link0_flowcontrol_f(u32 v) | ||
108 | { | ||
109 | return (v & 0x1U) << 13U; | ||
110 | } | ||
111 | static inline u32 nvlipt_err_uc_status_link0_flowcontrol_v(u32 r) | ||
112 | { | ||
113 | return (r >> 13U) & 0x1U; | ||
114 | } | ||
115 | static inline u32 nvlipt_err_uc_status_link0_responsetimeout_f(u32 v) | ||
116 | { | ||
117 | return (v & 0x1U) << 14U; | ||
118 | } | ||
119 | static inline u32 nvlipt_err_uc_status_link0_responsetimeout_v(u32 r) | ||
120 | { | ||
121 | return (r >> 14U) & 0x1U; | ||
122 | } | ||
123 | static inline u32 nvlipt_err_uc_status_link0_targeterror_f(u32 v) | ||
124 | { | ||
125 | return (v & 0x1U) << 15U; | ||
126 | } | ||
127 | static inline u32 nvlipt_err_uc_status_link0_targeterror_v(u32 r) | ||
128 | { | ||
129 | return (r >> 15U) & 0x1U; | ||
130 | } | ||
131 | static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x1U) << 16U; | ||
134 | } | ||
135 | static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_v(u32 r) | ||
136 | { | ||
137 | return (r >> 16U) & 0x1U; | ||
138 | } | ||
139 | static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 17U; | ||
142 | } | ||
143 | static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_v(u32 r) | ||
144 | { | ||
145 | return (r >> 17U) & 0x1U; | ||
146 | } | ||
147 | static inline u32 nvlipt_err_uc_status_link0_malformedpacket_f(u32 v) | ||
148 | { | ||
149 | return (v & 0x1U) << 18U; | ||
150 | } | ||
151 | static inline u32 nvlipt_err_uc_status_link0_malformedpacket_v(u32 r) | ||
152 | { | ||
153 | return (r >> 18U) & 0x1U; | ||
154 | } | ||
155 | static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_f(u32 v) | ||
156 | { | ||
157 | return (v & 0x1U) << 19U; | ||
158 | } | ||
159 | static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_v(u32 r) | ||
160 | { | ||
161 | return (r >> 19U) & 0x1U; | ||
162 | } | ||
163 | static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_f(u32 v) | ||
164 | { | ||
165 | return (v & 0x1U) << 20U; | ||
166 | } | ||
167 | static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_v(u32 r) | ||
168 | { | ||
169 | return (r >> 20U) & 0x1U; | ||
170 | } | ||
171 | static inline u32 nvlipt_err_uc_status_link0_ucinternal_f(u32 v) | ||
172 | { | ||
173 | return (v & 0x1U) << 22U; | ||
174 | } | ||
175 | static inline u32 nvlipt_err_uc_status_link0_ucinternal_v(u32 r) | ||
176 | { | ||
177 | return (r >> 22U) & 0x1U; | ||
178 | } | ||
179 | static inline u32 nvlipt_err_uc_mask_link0_r(void) | ||
180 | { | ||
181 | return 0x00000528U; | ||
182 | } | ||
183 | static inline u32 nvlipt_err_uc_severity_link0_r(void) | ||
184 | { | ||
185 | return 0x0000052cU; | ||
186 | } | ||
187 | static inline u32 nvlipt_err_uc_first_link0_r(void) | ||
188 | { | ||
189 | return 0x00000530U; | ||
190 | } | ||
191 | static inline u32 nvlipt_err_uc_advisory_link0_r(void) | ||
192 | { | ||
193 | return 0x00000534U; | ||
194 | } | ||
195 | static inline u32 nvlipt_err_c_status_link0_r(void) | ||
196 | { | ||
197 | return 0x00000538U; | ||
198 | } | ||
199 | static inline u32 nvlipt_err_c_mask_link0_r(void) | ||
200 | { | ||
201 | return 0x0000053cU; | ||
202 | } | ||
203 | static inline u32 nvlipt_err_c_first_link0_r(void) | ||
204 | { | ||
205 | return 0x00000540U; | ||
206 | } | ||
207 | static inline u32 nvlipt_err_control_link0_r(void) | ||
208 | { | ||
209 | return 0x00000544U; | ||
210 | } | ||
211 | static inline u32 nvlipt_err_control_link0_fatalenable_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x1U) << 1U; | ||
214 | } | ||
215 | static inline u32 nvlipt_err_control_link0_fatalenable_m(void) | ||
216 | { | ||
217 | return 0x1U << 1U; | ||
218 | } | ||
219 | static inline u32 nvlipt_err_control_link0_fatalenable_v(u32 r) | ||
220 | { | ||
221 | return (r >> 1U) & 0x1U; | ||
222 | } | ||
223 | static inline u32 nvlipt_err_control_link0_nonfatalenable_f(u32 v) | ||
224 | { | ||
225 | return (v & 0x1U) << 2U; | ||
226 | } | ||
227 | static inline u32 nvlipt_err_control_link0_nonfatalenable_m(void) | ||
228 | { | ||
229 | return 0x1U << 2U; | ||
230 | } | ||
231 | static inline u32 nvlipt_err_control_link0_nonfatalenable_v(u32 r) | ||
232 | { | ||
233 | return (r >> 2U) & 0x1U; | ||
234 | } | ||
235 | static inline u32 nvlipt_intr_control_common_r(void) | ||
236 | { | ||
237 | return 0x000004b0U; | ||
238 | } | ||
239 | static inline u32 nvlipt_intr_control_common_stallenable_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x1U) << 0U; | ||
242 | } | ||
243 | static inline u32 nvlipt_intr_control_common_stallenable_m(void) | ||
244 | { | ||
245 | return 0x1U << 0U; | ||
246 | } | ||
247 | static inline u32 nvlipt_intr_control_common_stallenable_v(u32 r) | ||
248 | { | ||
249 | return (r >> 0U) & 0x1U; | ||
250 | } | ||
251 | static inline u32 nvlipt_intr_control_common_nonstallenable_f(u32 v) | ||
252 | { | ||
253 | return (v & 0x1U) << 1U; | ||
254 | } | ||
255 | static inline u32 nvlipt_intr_control_common_nonstallenable_m(void) | ||
256 | { | ||
257 | return 0x1U << 1U; | ||
258 | } | ||
259 | static inline u32 nvlipt_intr_control_common_nonstallenable_v(u32 r) | ||
260 | { | ||
261 | return (r >> 1U) & 0x1U; | ||
262 | } | ||
263 | static inline u32 nvlipt_scratch_cold_r(void) | ||
264 | { | ||
265 | return 0x000007d4U; | ||
266 | } | ||
267 | static inline u32 nvlipt_scratch_cold_data_f(u32 v) | ||
268 | { | ||
269 | return (v & 0xffffffffU) << 0U; | ||
270 | } | ||
271 | static inline u32 nvlipt_scratch_cold_data_v(u32 r) | ||
272 | { | ||
273 | return (r >> 0U) & 0xffffffffU; | ||
274 | } | ||
275 | static inline u32 nvlipt_scratch_cold_data_init_v(void) | ||
276 | { | ||
277 | return 0xdeadbaadU; | ||
278 | } | ||
279 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h new file mode 100644 index 00000000..cc31b12b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h | |||
@@ -0,0 +1,95 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_nvtlc_gv100_h_ | ||
57 | #define _hw_nvtlc_gv100_h_ | ||
58 | |||
59 | static inline u32 nvtlc_tx_err_report_en_0_r(void) | ||
60 | { | ||
61 | return 0x00000708U; | ||
62 | } | ||
63 | static inline u32 nvtlc_rx_err_report_en_0_r(void) | ||
64 | { | ||
65 | return 0x00000f08U; | ||
66 | } | ||
67 | static inline u32 nvtlc_rx_err_report_en_1_r(void) | ||
68 | { | ||
69 | return 0x00000f20U; | ||
70 | } | ||
71 | static inline u32 nvtlc_tx_err_status_0_r(void) | ||
72 | { | ||
73 | return 0x00000700U; | ||
74 | } | ||
75 | static inline u32 nvtlc_rx_err_status_0_r(void) | ||
76 | { | ||
77 | return 0x00000f00U; | ||
78 | } | ||
79 | static inline u32 nvtlc_rx_err_status_1_r(void) | ||
80 | { | ||
81 | return 0x00000f18U; | ||
82 | } | ||
83 | static inline u32 nvtlc_tx_err_first_0_r(void) | ||
84 | { | ||
85 | return 0x00000714U; | ||
86 | } | ||
87 | static inline u32 nvtlc_rx_err_first_0_r(void) | ||
88 | { | ||
89 | return 0x00000f14U; | ||
90 | } | ||
91 | static inline u32 nvtlc_rx_err_first_1_r(void) | ||
92 | { | ||
93 | return 0x00000f2cU; | ||
94 | } | ||
95 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h index 6b3e8aa6..11333f43 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -128,6 +128,26 @@ static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) | |||
128 | { | 128 | { |
129 | return 0x20U; | 129 | return 0x20U; |
130 | } | 130 | } |
131 | static inline u32 ram_in_use_ver2_pt_format_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x1U) << 10U; | ||
134 | } | ||
135 | static inline u32 ram_in_use_ver2_pt_format_m(void) | ||
136 | { | ||
137 | return 0x1U << 10U; | ||
138 | } | ||
139 | static inline u32 ram_in_use_ver2_pt_format_w(void) | ||
140 | { | ||
141 | return 128U; | ||
142 | } | ||
143 | static inline u32 ram_in_use_ver2_pt_format_true_f(void) | ||
144 | { | ||
145 | return 0x400U; | ||
146 | } | ||
147 | static inline u32 ram_in_use_ver2_pt_format_false_f(void) | ||
148 | { | ||
149 | return 0x0U; | ||
150 | } | ||
131 | static inline u32 ram_in_big_page_size_f(u32 v) | 151 | static inline u32 ram_in_big_page_size_f(u32 v) |
132 | { | 152 | { |
133 | return (v & 0x1U) << 11U; | 153 | return (v & 0x1U) << 11U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h index da297b72..ff9c046c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -168,6 +168,14 @@ static inline u32 top_device_info_type_enum_lce_f(void) | |||
168 | { | 168 | { |
169 | return 0x4cU; | 169 | return 0x4cU; |
170 | } | 170 | } |
171 | static inline u32 top_device_info_type_enum_ioctrl_v(void) | ||
172 | { | ||
173 | return 0x00000012U; | ||
174 | } | ||
175 | static inline u32 top_device_info_type_enum_ioctrl_f(void) | ||
176 | { | ||
177 | return 0x48U; | ||
178 | } | ||
171 | static inline u32 top_device_info_engine_v(u32 r) | 179 | static inline u32 top_device_info_engine_v(u32 r) |
172 | { | 180 | { |
173 | return (r >> 5U) & 0x1U; | 181 | return (r >> 5U) & 0x1U; |
@@ -200,6 +208,10 @@ static inline u32 top_device_info_entry_data_v(void) | |||
200 | { | 208 | { |
201 | return 0x00000001U; | 209 | return 0x00000001U; |
202 | } | 210 | } |
211 | static inline u32 top_device_info_entry_engine_type_v(void) | ||
212 | { | ||
213 | return 0x00000003U; | ||
214 | } | ||
203 | static inline u32 top_device_info_data_type_v(u32 r) | 215 | static inline u32 top_device_info_data_type_v(u32 r) |
204 | { | 216 | { |
205 | return (r >> 30U) & 0x1U; | 217 | return (r >> 30U) & 0x1U; |
@@ -232,4 +244,92 @@ static inline u32 top_device_info_data_fault_id_valid_v(void) | |||
232 | { | 244 | { |
233 | return 0x00000001U; | 245 | return 0x00000001U; |
234 | } | 246 | } |
247 | static inline u32 top_nvhsclk_ctrl_r(void) | ||
248 | { | ||
249 | return 0x00022424U; | ||
250 | } | ||
251 | static inline u32 top_nvhsclk_ctrl_e_clk_nvl_f(u32 v) | ||
252 | { | ||
253 | return (v & 0x7U) << 0U; | ||
254 | } | ||
255 | static inline u32 top_nvhsclk_ctrl_e_clk_nvl_m(void) | ||
256 | { | ||
257 | return 0x7U << 0U; | ||
258 | } | ||
259 | static inline u32 top_nvhsclk_ctrl_e_clk_nvl_v(u32 r) | ||
260 | { | ||
261 | return (r >> 0U) & 0x7U; | ||
262 | } | ||
263 | static inline u32 top_nvhsclk_ctrl_e_clk_pcie_f(u32 v) | ||
264 | { | ||
265 | return (v & 0x1U) << 3U; | ||
266 | } | ||
267 | static inline u32 top_nvhsclk_ctrl_e_clk_pcie_m(void) | ||
268 | { | ||
269 | return 0x1U << 3U; | ||
270 | } | ||
271 | static inline u32 top_nvhsclk_ctrl_e_clk_pcie_v(u32 r) | ||
272 | { | ||
273 | return (r >> 3U) & 0x1U; | ||
274 | } | ||
275 | static inline u32 top_nvhsclk_ctrl_e_clk_core_f(u32 v) | ||
276 | { | ||
277 | return (v & 0x1U) << 4U; | ||
278 | } | ||
279 | static inline u32 top_nvhsclk_ctrl_e_clk_core_m(void) | ||
280 | { | ||
281 | return 0x1U << 4U; | ||
282 | } | ||
283 | static inline u32 top_nvhsclk_ctrl_e_clk_core_v(u32 r) | ||
284 | { | ||
285 | return (r >> 4U) & 0x1U; | ||
286 | } | ||
287 | static inline u32 top_nvhsclk_ctrl_rfu_f(u32 v) | ||
288 | { | ||
289 | return (v & 0xfU) << 5U; | ||
290 | } | ||
291 | static inline u32 top_nvhsclk_ctrl_rfu_m(void) | ||
292 | { | ||
293 | return 0xfU << 5U; | ||
294 | } | ||
295 | static inline u32 top_nvhsclk_ctrl_rfu_v(u32 r) | ||
296 | { | ||
297 | return (r >> 5U) & 0xfU; | ||
298 | } | ||
299 | static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_f(u32 v) | ||
300 | { | ||
301 | return (v & 0x7U) << 10U; | ||
302 | } | ||
303 | static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_m(void) | ||
304 | { | ||
305 | return 0x7U << 10U; | ||
306 | } | ||
307 | static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_v(u32 r) | ||
308 | { | ||
309 | return (r >> 10U) & 0x7U; | ||
310 | } | ||
311 | static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_f(u32 v) | ||
312 | { | ||
313 | return (v & 0x1U) << 9U; | ||
314 | } | ||
315 | static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_m(void) | ||
316 | { | ||
317 | return 0x1U << 9U; | ||
318 | } | ||
319 | static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_v(u32 r) | ||
320 | { | ||
321 | return (r >> 9U) & 0x1U; | ||
322 | } | ||
323 | static inline u32 top_nvhsclk_ctrl_swap_clk_core_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x1U) << 13U; | ||
326 | } | ||
327 | static inline u32 top_nvhsclk_ctrl_swap_clk_core_m(void) | ||
328 | { | ||
329 | return 0x1U << 13U; | ||
330 | } | ||
331 | static inline u32 top_nvhsclk_ctrl_swap_clk_core_v(u32 r) | ||
332 | { | ||
333 | return (r >> 13U) & 0x1U; | ||
334 | } | ||
235 | #endif | 335 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h new file mode 100644 index 00000000..9e7ceaff --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h | |||
@@ -0,0 +1,199 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_trim_gv100_h_ | ||
57 | #define _hw_trim_gv100_h_ | ||
58 | |||
59 | static inline u32 trim_sys_nvlink_uphy_cfg_r(void) | ||
60 | { | ||
61 | return 0x00132410U; | ||
62 | } | ||
63 | static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(u32 v) | ||
64 | { | ||
65 | return (v & 0x3ffU) << 0U; | ||
66 | } | ||
67 | static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m(void) | ||
68 | { | ||
69 | return 0x3ffU << 0U; | ||
70 | } | ||
71 | static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(u32 r) | ||
72 | { | ||
73 | return (r >> 0U) & 0x3ffU; | ||
74 | } | ||
75 | static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(u32 v) | ||
76 | { | ||
77 | return (v & 0x1U) << 12U; | ||
78 | } | ||
79 | static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m(void) | ||
80 | { | ||
81 | return 0x1U << 12U; | ||
82 | } | ||
83 | static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(u32 r) | ||
84 | { | ||
85 | return (r >> 12U) & 0x1U; | ||
86 | } | ||
87 | static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(u32 v) | ||
88 | { | ||
89 | return (v & 0xffU) << 16U; | ||
90 | } | ||
91 | static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m(void) | ||
92 | { | ||
93 | return 0xffU << 16U; | ||
94 | } | ||
95 | static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(u32 r) | ||
96 | { | ||
97 | return (r >> 16U) & 0xffU; | ||
98 | } | ||
99 | static inline u32 trim_sys_nvlink0_ctrl_r(void) | ||
100 | { | ||
101 | return 0x00132420U; | ||
102 | } | ||
103 | static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(u32 v) | ||
104 | { | ||
105 | return (v & 0x1U) << 0U; | ||
106 | } | ||
107 | static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m(void) | ||
108 | { | ||
109 | return 0x1U << 0U; | ||
110 | } | ||
111 | static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(u32 r) | ||
112 | { | ||
113 | return (r >> 0U) & 0x1U; | ||
114 | } | ||
115 | static inline u32 trim_sys_nvlink0_status_r(void) | ||
116 | { | ||
117 | return 0x00132424U; | ||
118 | } | ||
119 | static inline u32 trim_sys_nvlink0_status_pll_off_f(u32 v) | ||
120 | { | ||
121 | return (v & 0x1U) << 5U; | ||
122 | } | ||
123 | static inline u32 trim_sys_nvlink0_status_pll_off_m(void) | ||
124 | { | ||
125 | return 0x1U << 5U; | ||
126 | } | ||
127 | static inline u32 trim_sys_nvlink0_status_pll_off_v(u32 r) | ||
128 | { | ||
129 | return (r >> 5U) & 0x1U; | ||
130 | } | ||
131 | static inline u32 trim_sys_nvl_common_clk_alt_switch_r(void) | ||
132 | { | ||
133 | return 0x001371c4U; | ||
134 | } | ||
135 | static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_f(u32 v) | ||
136 | { | ||
137 | return (v & 0x3U) << 16U; | ||
138 | } | ||
139 | static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_m(void) | ||
140 | { | ||
141 | return 0x3U << 16U; | ||
142 | } | ||
143 | static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_v(u32 r) | ||
144 | { | ||
145 | return (r >> 16U) & 0x3U; | ||
146 | } | ||
147 | static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v(void) | ||
148 | { | ||
149 | return 0x00000003U; | ||
150 | } | ||
151 | static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f(void) | ||
152 | { | ||
153 | return 0x30000U; | ||
154 | } | ||
155 | static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v(void) | ||
156 | { | ||
157 | return 0x00000000U; | ||
158 | } | ||
159 | static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f(void) | ||
160 | { | ||
161 | return 0x0U; | ||
162 | } | ||
163 | static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_f(u32 v) | ||
164 | { | ||
165 | return (v & 0x3U) << 0U; | ||
166 | } | ||
167 | static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_m(void) | ||
168 | { | ||
169 | return 0x3U << 0U; | ||
170 | } | ||
171 | static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_v(u32 r) | ||
172 | { | ||
173 | return (r >> 0U) & 0x3U; | ||
174 | } | ||
175 | static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v(void) | ||
176 | { | ||
177 | return 0x00000000U; | ||
178 | } | ||
179 | static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_f(void) | ||
180 | { | ||
181 | return 0x0U; | ||
182 | } | ||
183 | static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_v(void) | ||
184 | { | ||
185 | return 0x00000002U; | ||
186 | } | ||
187 | static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f(void) | ||
188 | { | ||
189 | return 0x2U; | ||
190 | } | ||
191 | static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v(void) | ||
192 | { | ||
193 | return 0x00000003U; | ||
194 | } | ||
195 | static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f(void) | ||
196 | { | ||
197 | return 0x3U; | ||
198 | } | ||
199 | #endif | ||