diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-05-16 08:26:52 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-24 07:55:47 -0400 |
commit | 1eace20876b4136a1edf8287a9f37a693218efa8 (patch) | |
tree | 97f9b06306134792c4b33542f2c6888c5238e4c5 /drivers/gpu | |
parent | 8f4a590cf22fa9691953e9be0dca18b399228167 (diff) |
gpu: nvgpu: move gm20b clock register to platform file
We currently register gm20b clock operations gm20b_clk_ops
in function gm20b_register_gpcclk() which is in clk_gm20b.c
Since this is common clock framework and hence linux dependency,
move this clock registration to platform specific file
Note that all the clock operations remain in clk_gm20b.c.
APIs in platform file will eventually call operations
in clk_gm20b.c
Jira NVGPU-49
Change-Id: Ib0b0d9f4719b196d764825a7dddb08f1fbd7a567
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483091
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 76 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.h | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | 81 |
3 files changed, 98 insertions, 72 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index f1f75b74..31ec419a 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1131,13 +1131,7 @@ static int clk_disable_gpcpll(struct gk20a *g, int allow_slide) | |||
1131 | return 0; | 1131 | return 0; |
1132 | } | 1132 | } |
1133 | 1133 | ||
1134 | static int gm20b_init_clk_reset_enable_hw(struct gk20a *g) | 1134 | int gm20b_init_clk_setup_sw(struct gk20a *g) |
1135 | { | ||
1136 | gk20a_dbg_fn(""); | ||
1137 | return 0; | ||
1138 | } | ||
1139 | |||
1140 | static int gm20b_init_clk_setup_sw(struct gk20a *g) | ||
1141 | { | 1135 | { |
1142 | struct clk_gk20a *clk = &g->clk; | 1136 | struct clk_gk20a *clk = &g->clk; |
1143 | unsigned long safe_rate; | 1137 | unsigned long safe_rate; |
@@ -1238,13 +1232,11 @@ fail: | |||
1238 | } | 1232 | } |
1239 | 1233 | ||
1240 | 1234 | ||
1241 | #ifdef CONFIG_COMMON_CLK | ||
1242 | static int set_pll_freq(struct gk20a *g, int allow_slide); | 1235 | static int set_pll_freq(struct gk20a *g, int allow_slide); |
1243 | static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq); | 1236 | static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq); |
1244 | 1237 | ||
1245 | static int gm20b_clk_prepare(struct clk_hw *hw) | 1238 | int gm20b_clk_prepare(struct clk_gk20a *clk) |
1246 | { | 1239 | { |
1247 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
1248 | int ret = 0; | 1240 | int ret = 0; |
1249 | 1241 | ||
1250 | nvgpu_mutex_acquire(&clk->clk_mutex); | 1242 | nvgpu_mutex_acquire(&clk->clk_mutex); |
@@ -1254,34 +1246,27 @@ static int gm20b_clk_prepare(struct clk_hw *hw) | |||
1254 | return ret; | 1246 | return ret; |
1255 | } | 1247 | } |
1256 | 1248 | ||
1257 | static void gm20b_clk_unprepare(struct clk_hw *hw) | 1249 | void gm20b_clk_unprepare(struct clk_gk20a *clk) |
1258 | { | 1250 | { |
1259 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
1260 | |||
1261 | nvgpu_mutex_acquire(&clk->clk_mutex); | 1251 | nvgpu_mutex_acquire(&clk->clk_mutex); |
1262 | if (clk->gpc_pll.enabled && clk->clk_hw_on) | 1252 | if (clk->gpc_pll.enabled && clk->clk_hw_on) |
1263 | clk_disable_gpcpll(clk->g, 1); | 1253 | clk_disable_gpcpll(clk->g, 1); |
1264 | nvgpu_mutex_release(&clk->clk_mutex); | 1254 | nvgpu_mutex_release(&clk->clk_mutex); |
1265 | } | 1255 | } |
1266 | 1256 | ||
1267 | static int gm20b_clk_is_prepared(struct clk_hw *hw) | 1257 | int gm20b_clk_is_prepared(struct clk_gk20a *clk) |
1268 | { | 1258 | { |
1269 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
1270 | |||
1271 | return clk->gpc_pll.enabled && clk->clk_hw_on; | 1259 | return clk->gpc_pll.enabled && clk->clk_hw_on; |
1272 | } | 1260 | } |
1273 | 1261 | ||
1274 | static unsigned long gm20b_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) | 1262 | unsigned long gm20b_recalc_rate(struct clk_gk20a *clk, unsigned long parent_rate) |
1275 | { | 1263 | { |
1276 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
1277 | |||
1278 | return rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | 1264 | return rate_gpc2clk_to_gpu(clk->gpc_pll.freq); |
1279 | } | 1265 | } |
1280 | 1266 | ||
1281 | static int gm20b_gpcclk_set_rate(struct clk_hw *hw, unsigned long rate, | 1267 | int gm20b_gpcclk_set_rate(struct clk_gk20a *clk, unsigned long rate, |
1282 | unsigned long parent_rate) | 1268 | unsigned long parent_rate) |
1283 | { | 1269 | { |
1284 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
1285 | u32 old_freq; | 1270 | u32 old_freq; |
1286 | int ret = -ENODATA; | 1271 | int ret = -ENODATA; |
1287 | 1272 | ||
@@ -1295,10 +1280,9 @@ static int gm20b_gpcclk_set_rate(struct clk_hw *hw, unsigned long rate, | |||
1295 | return ret; | 1280 | return ret; |
1296 | } | 1281 | } |
1297 | 1282 | ||
1298 | static long gm20b_round_rate(struct clk_hw *hw, unsigned long rate, | 1283 | long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate, |
1299 | unsigned long *parent_rate) | 1284 | unsigned long *parent_rate) |
1300 | { | 1285 | { |
1301 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
1302 | u32 freq; | 1286 | u32 freq; |
1303 | struct pll tmp_pll; | 1287 | struct pll tmp_pll; |
1304 | unsigned long maxrate; | 1288 | unsigned long maxrate; |
@@ -1321,48 +1305,6 @@ static long gm20b_round_rate(struct clk_hw *hw, unsigned long rate, | |||
1321 | return rate_gpc2clk_to_gpu(tmp_pll.freq); | 1305 | return rate_gpc2clk_to_gpu(tmp_pll.freq); |
1322 | } | 1306 | } |
1323 | 1307 | ||
1324 | static const struct clk_ops gm20b_clk_ops = { | ||
1325 | .prepare = gm20b_clk_prepare, | ||
1326 | .unprepare = gm20b_clk_unprepare, | ||
1327 | .is_prepared = gm20b_clk_is_prepared, | ||
1328 | .recalc_rate = gm20b_recalc_rate, | ||
1329 | .set_rate = gm20b_gpcclk_set_rate, | ||
1330 | .round_rate = gm20b_round_rate, | ||
1331 | }; | ||
1332 | |||
1333 | int gm20b_register_gpcclk(struct gk20a *g) { | ||
1334 | const char *parent_name = "pllg_ref"; | ||
1335 | struct clk_gk20a *clk = &g->clk; | ||
1336 | struct clk_init_data init; | ||
1337 | struct clk *c; | ||
1338 | int err = 0; | ||
1339 | |||
1340 | err = gm20b_init_clk_setup_sw(g); | ||
1341 | if (err) | ||
1342 | return err; | ||
1343 | |||
1344 | init.name = "gpcclk"; | ||
1345 | init.ops = &gm20b_clk_ops; | ||
1346 | init.parent_names = &parent_name; | ||
1347 | init.num_parents = 1; | ||
1348 | init.flags = 0; | ||
1349 | |||
1350 | /* Data in .init is copied by clk_register(), so stack variable OK */ | ||
1351 | clk->hw.init = &init; | ||
1352 | c = clk_register(g->dev, &clk->hw); | ||
1353 | if (IS_ERR(c)) { | ||
1354 | nvgpu_err(g, "Failed to register GPCPLL clock"); | ||
1355 | return -EINVAL; | ||
1356 | } | ||
1357 | |||
1358 | clk->g = g; | ||
1359 | clk_register_clkdev(c, "gpcclk", "gpcclk"); | ||
1360 | |||
1361 | return err; | ||
1362 | } | ||
1363 | #endif /* CONFIG_COMMON_CLK */ | ||
1364 | |||
1365 | |||
1366 | static int gm20b_init_clk_setup_hw(struct gk20a *g) | 1308 | static int gm20b_init_clk_setup_hw(struct gk20a *g) |
1367 | { | 1309 | { |
1368 | u32 data; | 1310 | u32 data; |
@@ -1475,10 +1417,6 @@ static int gm20b_init_clk_support(struct gk20a *g) | |||
1475 | 1417 | ||
1476 | gk20a_dbg_fn(""); | 1418 | gk20a_dbg_fn(""); |
1477 | 1419 | ||
1478 | err = gm20b_init_clk_reset_enable_hw(g); | ||
1479 | if (err) | ||
1480 | return err; | ||
1481 | |||
1482 | nvgpu_mutex_acquire(&clk->clk_mutex); | 1420 | nvgpu_mutex_acquire(&clk->clk_mutex); |
1483 | clk->clk_hw_on = true; | 1421 | clk->clk_hw_on = true; |
1484 | 1422 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h index 5746165e..f7912345 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h | |||
@@ -23,8 +23,15 @@ | |||
23 | 23 | ||
24 | void gm20b_init_clk_ops(struct gpu_ops *gops); | 24 | void gm20b_init_clk_ops(struct gpu_ops *gops); |
25 | 25 | ||
26 | #ifdef CONFIG_COMMON_CLK | 26 | int gm20b_init_clk_setup_sw(struct gk20a *g); |
27 | int gm20b_register_gpcclk(struct gk20a *g); | 27 | |
28 | #endif | 28 | int gm20b_clk_prepare(struct clk_gk20a *clk); |
29 | void gm20b_clk_unprepare(struct clk_gk20a *clk); | ||
30 | int gm20b_clk_is_prepared(struct clk_gk20a *clk); | ||
31 | unsigned long gm20b_recalc_rate(struct clk_gk20a *clk, unsigned long parent_rate); | ||
32 | int gm20b_gpcclk_set_rate(struct clk_gk20a *clk, unsigned long rate, | ||
33 | unsigned long parent_rate); | ||
34 | long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate, | ||
35 | unsigned long *parent_rate); | ||
29 | 36 | ||
30 | #endif /* _NVHOST_CLK_GM20B_H_ */ | 37 | #endif /* _NVHOST_CLK_GM20B_H_ */ |
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c index a8a1451a..d6e448d8 100644 --- a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | |||
@@ -753,6 +753,87 @@ void gk20a_tegra_init_secure_alloc(struct gk20a *g) | |||
753 | g->ops.mm.secure_alloc = gk20a_tegra_secure_alloc; | 753 | g->ops.mm.secure_alloc = gk20a_tegra_secure_alloc; |
754 | } | 754 | } |
755 | 755 | ||
756 | #ifdef CONFIG_COMMON_CLK | ||
757 | static int gm20b_clk_prepare_ops(struct clk_hw *hw) | ||
758 | { | ||
759 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
760 | return gm20b_clk_prepare(clk); | ||
761 | } | ||
762 | |||
763 | static void gm20b_clk_unprepare_ops(struct clk_hw *hw) | ||
764 | { | ||
765 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
766 | gm20b_clk_unprepare(clk); | ||
767 | } | ||
768 | |||
769 | static int gm20b_clk_is_prepared_ops(struct clk_hw *hw) | ||
770 | { | ||
771 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
772 | return gm20b_clk_is_prepared(clk); | ||
773 | } | ||
774 | |||
775 | static unsigned long gm20b_recalc_rate_ops(struct clk_hw *hw, unsigned long parent_rate) | ||
776 | { | ||
777 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
778 | return gm20b_recalc_rate(clk, parent_rate); | ||
779 | } | ||
780 | |||
781 | static int gm20b_gpcclk_set_rate_ops(struct clk_hw *hw, unsigned long rate, | ||
782 | unsigned long parent_rate) | ||
783 | { | ||
784 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
785 | return gm20b_gpcclk_set_rate(clk, rate, parent_rate); | ||
786 | } | ||
787 | |||
788 | static long gm20b_round_rate_ops(struct clk_hw *hw, unsigned long rate, | ||
789 | unsigned long *parent_rate) | ||
790 | { | ||
791 | struct clk_gk20a *clk = to_clk_gk20a(hw); | ||
792 | return gm20b_round_rate(clk, rate, parent_rate); | ||
793 | } | ||
794 | |||
795 | static const struct clk_ops gm20b_clk_ops = { | ||
796 | .prepare = gm20b_clk_prepare_ops, | ||
797 | .unprepare = gm20b_clk_unprepare_ops, | ||
798 | .is_prepared = gm20b_clk_is_prepared_ops, | ||
799 | .recalc_rate = gm20b_recalc_rate_ops, | ||
800 | .set_rate = gm20b_gpcclk_set_rate_ops, | ||
801 | .round_rate = gm20b_round_rate_ops, | ||
802 | }; | ||
803 | |||
804 | static int gm20b_register_gpcclk(struct gk20a *g) | ||
805 | { | ||
806 | const char *parent_name = "pllg_ref"; | ||
807 | struct clk_gk20a *clk = &g->clk; | ||
808 | struct clk_init_data init; | ||
809 | struct clk *c; | ||
810 | int err = 0; | ||
811 | |||
812 | err = gm20b_init_clk_setup_sw(g); | ||
813 | if (err) | ||
814 | return err; | ||
815 | |||
816 | init.name = "gpcclk"; | ||
817 | init.ops = &gm20b_clk_ops; | ||
818 | init.parent_names = &parent_name; | ||
819 | init.num_parents = 1; | ||
820 | init.flags = 0; | ||
821 | |||
822 | /* Data in .init is copied by clk_register(), so stack variable OK */ | ||
823 | clk->hw.init = &init; | ||
824 | c = clk_register(g->dev, &clk->hw); | ||
825 | if (IS_ERR(c)) { | ||
826 | nvgpu_err(g, "Failed to register GPCPLL clock"); | ||
827 | return -EINVAL; | ||
828 | } | ||
829 | |||
830 | clk->g = g; | ||
831 | clk_register_clkdev(c, "gpcclk", "gpcclk"); | ||
832 | |||
833 | return err; | ||
834 | } | ||
835 | #endif /* CONFIG_COMMON_CLK */ | ||
836 | |||
756 | static int gk20a_tegra_probe(struct device *dev) | 837 | static int gk20a_tegra_probe(struct device *dev) |
757 | { | 838 | { |
758 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 839 | struct gk20a_platform *platform = dev_get_drvdata(dev); |