diff options
author | Deepak Goyal <dgoyal@nvidia.com> | 2017-06-08 01:51:52 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-08 10:54:24 -0400 |
commit | 1dfcf1833ba3e8fa58d0ad6ecb189db32c6b986f (patch) | |
tree | 4bf591fb2b7e07cf0c008092615953c6c21963eb /drivers/gpu | |
parent | 0ad7f1d9aa18d959abf3cba6ca4e532fc9246a31 (diff) |
gpu: nvgpu: Update PMU firmware version.
This patch also updates PMU cmdline args as
required by updated firmware.
GPUT19x-30
Change-Id: I44214007046081a44acc7284eb2854d0548a8da8
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1498188
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmu.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | 11 |
4 files changed, 19 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index f296b57c..4e416f67 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -205,6 +205,11 @@ static u32 pmu_cmdline_size_v5(struct nvgpu_pmu *pmu) | |||
205 | return sizeof(struct pmu_cmdline_args_v5); | 205 | return sizeof(struct pmu_cmdline_args_v5); |
206 | } | 206 | } |
207 | 207 | ||
208 | static u32 pmu_cmdline_size_v6(struct nvgpu_pmu *pmu) | ||
209 | { | ||
210 | return sizeof(struct pmu_cmdline_args_v6); | ||
211 | } | ||
212 | |||
208 | static void set_pmu_cmdline_args_cpufreq_v5(struct nvgpu_pmu *pmu, u32 freq) | 213 | static void set_pmu_cmdline_args_cpufreq_v5(struct nvgpu_pmu *pmu, u32 freq) |
209 | { | 214 | { |
210 | pmu->args_v5.cpu_freq_hz = 204000000; | 215 | pmu->args_v5.cpu_freq_hz = 204000000; |
@@ -1586,7 +1591,7 @@ int gk20a_init_pmu(struct nvgpu_pmu *pmu) | |||
1586 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1591 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; |
1587 | g->ops.pmu_ver.is_pmu_zbc_save_supported = false; | 1592 | g->ops.pmu_ver.is_pmu_zbc_save_supported = false; |
1588 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1593 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1589 | pmu_cmdline_size_v5; | 1594 | pmu_cmdline_size_v6; |
1590 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1595 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
1591 | set_pmu_cmdline_args_cpufreq_v5; | 1596 | set_pmu_cmdline_args_cpufreq_v5; |
1592 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode = | 1597 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode = |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 3941d90f..24bc5822 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -30,7 +30,7 @@ struct nvgpu_firmware; | |||
30 | 30 | ||
31 | #define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) | 31 | #define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) |
32 | 32 | ||
33 | #define APP_VERSION_NC_3 21688026 | 33 | #define APP_VERSION_NC_3 22204331 |
34 | #define APP_VERSION_NC_2 20429989 | 34 | #define APP_VERSION_NC_2 20429989 |
35 | #define APP_VERSION_NC_1 20313802 | 35 | #define APP_VERSION_NC_1 20313802 |
36 | #define APP_VERSION_NC_0 20360931 | 36 | #define APP_VERSION_NC_0 20360931 |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 0fcc5710..687e00ae 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h | |||
@@ -314,6 +314,7 @@ struct nvgpu_pmu { | |||
314 | struct pmu_cmdline_args_v3 args_v3; | 314 | struct pmu_cmdline_args_v3 args_v3; |
315 | struct pmu_cmdline_args_v4 args_v4; | 315 | struct pmu_cmdline_args_v4 args_v4; |
316 | struct pmu_cmdline_args_v5 args_v5; | 316 | struct pmu_cmdline_args_v5 args_v5; |
317 | struct pmu_cmdline_args_v6 args_v6; | ||
317 | }; | 318 | }; |
318 | unsigned long perfmon_events_cnt; | 319 | unsigned long perfmon_events_cnt; |
319 | bool perfmon_sampling_enabled; | 320 | bool perfmon_sampling_enabled; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h index 6df92c1d..a8897034 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | |||
@@ -77,6 +77,17 @@ struct pmu_cmdline_args_v5 { | |||
77 | u32 dummy; | 77 | u32 dummy; |
78 | }; | 78 | }; |
79 | 79 | ||
80 | struct pmu_cmdline_args_v6 { | ||
81 | u32 cpu_freq_hz; | ||
82 | struct flcn_mem_desc_v0 trace_buf; | ||
83 | u8 secure_mode; | ||
84 | u8 raise_priv_sec; | ||
85 | struct flcn_mem_desc_v0 gc6_ctx; | ||
86 | struct flcn_mem_desc_v0 gc6_bsod_ctx; | ||
87 | struct flcn_mem_desc_v0 init_data_dma_info; | ||
88 | u32 dummy; | ||
89 | }; | ||
90 | |||
80 | /* GPU ID */ | 91 | /* GPU ID */ |
81 | #define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2 | 92 | #define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2 |
82 | #define PMU_SHA1_GID_SIGNATURE_SIZE 4 | 93 | #define PMU_SHA1_GID_SIGNATURE_SIZE 4 |