diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2015-09-12 02:20:19 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-09-15 17:32:55 -0400 |
commit | 1b2faa54260def17037ac6f04e3f32361c5a8f92 (patch) | |
tree | cc9075ccdef77ab72ffda6571246fa9c30126649 /drivers/gpu | |
parent | 1de62619720b86f07338402d367e278ca820c32d (diff) |
gpu: nvgpu: gpccs load using priv load
- load gppcs with force priv load method.
Bug n/a
Change-Id: I3566375f51da701c90e0f5f873c71953f0113443
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798144
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 6 |
2 files changed, 9 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 152b9637..dd48f34f 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -511,12 +511,15 @@ static int pmu_populate_loader_cfg(struct gk20a *g, | |||
511 | /* Populate the loader_config state*/ | 511 | /* Populate the loader_config state*/ |
512 | ldr_cfg->dma_idx = GK20A_PMU_DMAIDX_UCODE; | 512 | ldr_cfg->dma_idx = GK20A_PMU_DMAIDX_UCODE; |
513 | ldr_cfg->code_dma_base = addr_code; | 513 | ldr_cfg->code_dma_base = addr_code; |
514 | ldr_cfg->code_dma_base1 = 0x0; | ||
514 | ldr_cfg->code_size_total = desc->app_size; | 515 | ldr_cfg->code_size_total = desc->app_size; |
515 | ldr_cfg->code_size_to_load = desc->app_resident_code_size; | 516 | ldr_cfg->code_size_to_load = desc->app_resident_code_size; |
516 | ldr_cfg->code_entry_point = desc->app_imem_entry; | 517 | ldr_cfg->code_entry_point = desc->app_imem_entry; |
517 | ldr_cfg->data_dma_base = addr_data; | 518 | ldr_cfg->data_dma_base = addr_data; |
519 | ldr_cfg->data_dma_base1 = 0; | ||
518 | ldr_cfg->data_size = desc->app_resident_data_size; | 520 | ldr_cfg->data_size = desc->app_resident_data_size; |
519 | ldr_cfg->overlay_dma_base = addr_code; | 521 | ldr_cfg->overlay_dma_base = addr_code; |
522 | ldr_cfg->overlay_dma_base1 = 0x0; | ||
520 | 523 | ||
521 | /* Update the argc/argv members*/ | 524 | /* Update the argc/argv members*/ |
522 | ldr_cfg->argc = 1; | 525 | ldr_cfg->argc = 1; |
@@ -836,7 +839,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, | |||
836 | } | 839 | } |
837 | if (falcon_id == LSF_FALCON_ID_GPCCS) { | 840 | if (falcon_id == LSF_FALCON_ID_GPCCS) { |
838 | pnode->lsb_header.flags |= | 841 | pnode->lsb_header.flags |= |
839 | NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE; | 842 | NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE; |
840 | } | 843 | } |
841 | } | 844 | } |
842 | } | 845 | } |
@@ -1082,6 +1085,7 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g) | |||
1082 | bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT; | 1085 | bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT; |
1083 | bl_dmem_desc->code_dma_base = | 1086 | bl_dmem_desc->code_dma_base = |
1084 | (unsigned int)(((u64)acr->acr_ucode.gpu_va >> 8)); | 1087 | (unsigned int)(((u64)acr->acr_ucode.gpu_va >> 8)); |
1088 | bl_dmem_desc->code_dma_base1 = 0x0; | ||
1085 | bl_dmem_desc->non_sec_code_off = acr_ucode_header_t210_load[0]; | 1089 | bl_dmem_desc->non_sec_code_off = acr_ucode_header_t210_load[0]; |
1086 | bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1]; | 1090 | bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1]; |
1087 | bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5]; | 1091 | bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5]; |
@@ -1090,6 +1094,7 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g) | |||
1090 | bl_dmem_desc->data_dma_base = | 1094 | bl_dmem_desc->data_dma_base = |
1091 | bl_dmem_desc->code_dma_base + | 1095 | bl_dmem_desc->code_dma_base + |
1092 | ((acr_ucode_header_t210_load[2]) >> 8); | 1096 | ((acr_ucode_header_t210_load[2]) >> 8); |
1097 | bl_dmem_desc->data_dma_base1 = 0x0; | ||
1093 | bl_dmem_desc->data_size = acr_ucode_header_t210_load[3]; | 1098 | bl_dmem_desc->data_size = acr_ucode_header_t210_load[3]; |
1094 | } else | 1099 | } else |
1095 | acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0; | 1100 | acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0; |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index fd9cf2ec..d6315c2d 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -220,9 +220,9 @@ struct loader_config { | |||
220 | u32 overlay_dma_base; /*<! upper 32-bits of the 40-bit dma address*/ | 220 | u32 overlay_dma_base; /*<! upper 32-bits of the 40-bit dma address*/ |
221 | u32 argc; | 221 | u32 argc; |
222 | u32 argv; | 222 | u32 argv; |
223 | u32 code_dma_base1; /*<! upper 7 bits of 47-bit dma address*/ | 223 | u16 code_dma_base1; /*<! upper 7 bits of 47-bit dma address*/ |
224 | u32 data_dma_base1; /*<! upper 7 bits of 47-bit dma address*/ | 224 | u16 data_dma_base1; /*<! upper 7 bits of 47-bit dma address*/ |
225 | u32 overlay_dma_base1; /*<! upper 7 bits of the 47-bit dma address*/ | 225 | u16 overlay_dma_base1; /*<! upper 7 bits of the 47-bit dma address*/ |
226 | }; | 226 | }; |
227 | 227 | ||
228 | /*! | 228 | /*! |