gpu: nvgpu: define EVENT_IDs in common code

All the event ids NVGPU_IOCTL_CHANNEL_EVENT_ID_* are defined in linux
specific user header uapi/linux/nvgpu.h and can't be used in common
code

Hence add new definitions of type NVGPU_EVENT_ID_* for all the events
in common code and use them wherever required in common code

For future additions to event ids, we need to update both
NVGPU_IOCTL_CHANNEL_EVENT_ID_* and NVGPU_EVENT_ID_* fields

Also add new API nvgpu_event_id_to_ioctl_channel_event_id() to convert
common event_id of the form NVGPU_EVENT_ID_* to Linux specific event_id
of the form NVGPU_IOCTL_CHANNEL_EVENT_ID_*
Use this API in gk20a_channel/tsg_event_id_post_event() to get correct
event_id

Jira NVGPU-259

Change-Id: I15a7f41181fdbb8f1876f88bbcd044447d88325f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1591434
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

7 files changed, 61 insertions, 14 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
index 44f662cb..9a867bcb 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
@@ -21,6 +21,8 @@
 #include <linux/anon_inodes.h>
 #include <linux/dma-buf.h>
 #include <linux/poll.h>
+#include <uapi/linux/nvgpu.h>
+#include <uapi/linux/nvgpu-t18x.h>
 
 #include <nvgpu/semaphore.h>
 #include <nvgpu/timers.h>
@@ -689,12 +691,41 @@ static int gk20a_channel_get_event_data_from_id(struct channel_gk20a *ch,
         }
 }
 
+/*
+ * Convert common event_id of the form NVGPU_EVENT_ID_* to Linux specific
+ * event_id of the form NVGPU_IOCTL_CHANNEL_EVENT_ID_* which is used in IOCTLs
+ */
+u32 nvgpu_event_id_to_ioctl_channel_event_id(u32 event_id)
+{
+        switch (event_id) {
+        case NVGPU_EVENT_ID_BPT_INT:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT;
+        case NVGPU_EVENT_ID_BPT_PAUSE:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE;
+        case NVGPU_EVENT_ID_BLOCKING_SYNC:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC;
+        case NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED;
+        case NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE;
+        case NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN;
+        }
+
+        return NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX;
+}
+
 void gk20a_channel_event_id_post_event(struct channel_gk20a *ch,
-                                       u32 event_id)
+                                       u32 __event_id)
 {
         struct gk20a_event_id_data *event_id_data;
+        u32 event_id;
         int err = 0;
 
+        event_id = nvgpu_event_id_to_ioctl_channel_event_id(__event_id);
+        if (event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX)
+                return;
+
         err = gk20a_channel_get_event_data_from_id(ch, event_id,
                                                 &event_id_data);
         if (err)
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.h b/drivers/gpu/nvgpu/common/linux/ioctl_channel.h
index 1aac04aa..8cfce7e1 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.h
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.h
@@ -23,4 +23,5 @@ int gk20a_channel_open_ioctl(struct gk20a *g,
 extern const struct file_operations gk20a_event_id_ops;
 extern const struct file_operations gk20a_channel_ops;
 
+u32 nvgpu_event_id_to_ioctl_channel_event_id(u32 event_id);
 #endif
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
index 2570886d..681a5e66 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
@@ -80,11 +80,16 @@ static int gk20a_tsg_get_event_data_from_id(struct tsg_gk20a *tsg,
 }
 
 void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg,
-                                       int event_id)
+                                       int __event_id)
 {
         struct gk20a_event_id_data *event_id_data;
+        u32 event_id;
         int err = 0;
 
+        event_id = nvgpu_event_id_to_ioctl_channel_event_id(__event_id);
+        if (event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX)
+                return;
+
         err = gk20a_tsg_get_event_data_from_id(tsg, event_id,
                                                 &event_id_data);
         if (err)
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index c938ba6b..805902eb 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -2395,10 +2395,10 @@ void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events)
                                                         &g->fifo.tsg[c->tsgid];
 
                                                 gk20a_tsg_event_id_post_event(tsg,
-                                                    NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC);
+                                                    NVGPU_EVENT_ID_BLOCKING_SYNC);
                                         } else {
                                                 gk20a_channel_event_id_post_event(c,
-                                                    NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC);
+                                                    NVGPU_EVENT_ID_BLOCKING_SYNC);
                                         }
                                 }
                                 /*
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 2a20c2d9..f7db1ffa 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5275,10 +5275,10 @@ static int gk20a_gr_handle_semaphore_pending(struct gk20a *g,
                 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
 
                 gk20a_tsg_event_id_post_event(tsg,
-                        NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN);
+                        NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN);
         } else {
                 gk20a_channel_event_id_post_event(ch,
-                        NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN);
+                        NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN);
         }
 
         nvgpu_cond_broadcast(&ch->semaphore_wq);
@@ -5824,10 +5824,10 @@ static int gk20a_gr_post_bpt_events(struct gk20a *g, struct channel_gk20a *ch,
                         struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
 
                         gk20a_tsg_event_id_post_event(tsg,
-                                NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT);
+                                NVGPU_EVENT_ID_BPT_INT);
                 } else {
                         gk20a_channel_event_id_post_event(ch,
-                                NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT);
+                                NVGPU_EVENT_ID_BPT_INT);
                 }
         }
         if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f()) {
@@ -5835,10 +5835,10 @@ static int gk20a_gr_post_bpt_events(struct gk20a *g, struct channel_gk20a *ch,
                         struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
 
                         gk20a_tsg_event_id_post_event(tsg,
-                                NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE);
+                                NVGPU_EVENT_ID_BPT_PAUSE);
                 } else {
                         gk20a_channel_event_id_post_event(ch,
-                                NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE);
+                                NVGPU_EVENT_ID_BPT_PAUSE);
                 }
         }
 
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 8a044728..d411a2fa 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -124,6 +124,16 @@ enum {
         BLCG_AUTO       /* clk will run when non-idle, standard blcg mode */
 };
 
+enum {
+        NVGPU_EVENT_ID_BPT_INT = 0,
+        NVGPU_EVENT_ID_BPT_PAUSE,
+        NVGPU_EVENT_ID_BLOCKING_SYNC,
+        NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED,
+        NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE,
+        NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN,
+        NVGPU_EVENT_ID_MAX,
+};
+
 #ifndef GR_GO_IDLE_BUNDLE
 #define GR_GO_IDLE_BUNDLE       0x0000e100 /* --V-B */
 #endif
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 78be072f..f1180750 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1779,10 +1779,10 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
                 struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid];
 
                 gk20a_tsg_event_id_post_event(tsg,
-                                NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED);
+                                NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED);
         } else {
                 gk20a_channel_event_id_post_event(fault_ch,
-                                NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED);
+                                NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED);
         }
 
         return 0;
@@ -1990,10 +1990,10 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g,
                         struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
 
                         gk20a_tsg_event_id_post_event(tsg,
-                                NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE);
+                                NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE);
                 } else {
                         gk20a_channel_event_id_post_event(ch,
-                                NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE);
+                                NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE);
                 }
 
                 gk20a_channel_put(ch);