diff options
author | Richard Zhao <rizhao@nvidia.com> | 2015-11-16 13:26:23 -0500 |
---|---|---|
committer | Vladislav Buzov <vbuzov@nvidia.com> | 2015-11-23 17:31:02 -0500 |
commit | 1246629c19485d9a9e6fc2c2e7d1f86f65b9516d (patch) | |
tree | b17a44c7d47ffe20ef0d6e4e6bec8acbec9ba5ad /drivers/gpu | |
parent | 8ec63298789a0912b9cbd90ee47c76f0701f0dca (diff) |
gpu: nvgpu: abstract set mmu debug mode
Add new operaton g->ops.mm.set_debug_mode and let other places
that set debug mode call this callback.
It's preparing for adding vgpu set mmu debug mode hook.
JIRA VFND-1005
Bug 1594604
Change-Id: I1d227a0c0f96adb0035ae16ae1f4fbfa739bf0a7
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/833497
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mm_gm20b.c | 26 |
6 files changed, 67 insertions, 36 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index 18567064..4f33c78f 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -313,33 +313,17 @@ static int nvgpu_gpu_ioctl_set_mmu_debug_mode( | |||
313 | struct gk20a *g, | 313 | struct gk20a *g, |
314 | struct nvgpu_gpu_mmu_debug_mode_args *args) | 314 | struct nvgpu_gpu_mmu_debug_mode_args *args) |
315 | { | 315 | { |
316 | int err = 0; | 316 | if (gk20a_busy(g->dev)) { |
317 | u32 reg_val, mmu_debug_ctrl; | ||
318 | |||
319 | err = gk20a_busy(g->dev); | ||
320 | if (err) { | ||
321 | gk20a_err(dev_from_gk20a(g), "failed to power on gpu\n"); | 317 | gk20a_err(dev_from_gk20a(g), "failed to power on gpu\n"); |
322 | return -EINVAL; | 318 | return -EINVAL; |
323 | } | 319 | } |
324 | 320 | ||
325 | mutex_lock(&g->dbg_sessions_lock); | 321 | mutex_lock(&g->dbg_sessions_lock); |
326 | 322 | g->ops.mm.set_debug_mode(g, args->state == 1); | |
327 | if (args->state == 1) { | ||
328 | mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); | ||
329 | g->mmu_debug_ctrl = true; | ||
330 | } else { | ||
331 | mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); | ||
332 | g->mmu_debug_ctrl = false; | ||
333 | } | ||
334 | |||
335 | reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
336 | reg_val = set_field(reg_val, | ||
337 | fb_mmu_debug_ctrl_debug_m(), mmu_debug_ctrl); | ||
338 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | ||
339 | |||
340 | mutex_unlock(&g->dbg_sessions_lock); | 323 | mutex_unlock(&g->dbg_sessions_lock); |
324 | |||
341 | gk20a_idle(g->dev); | 325 | gk20a_idle(g->dev); |
342 | return err; | 326 | return 0; |
343 | } | 327 | } |
344 | 328 | ||
345 | static int nvgpu_gpu_ioctl_set_debug_mode( | 329 | static int nvgpu_gpu_ioctl_set_debug_mode( |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index dfc7d34c..7ac600c0 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -747,21 +747,6 @@ static int gk20a_detect_chip(struct gk20a *g) | |||
747 | return gpu_init_hal(g); | 747 | return gpu_init_hal(g); |
748 | } | 748 | } |
749 | 749 | ||
750 | static void gk20a_pm_restore_debug_setting(struct gk20a *g) | ||
751 | { | ||
752 | u32 mmu_debug_ctrl; | ||
753 | |||
754 | /* restore mmu debug state */ | ||
755 | if (g->mmu_debug_ctrl) | ||
756 | mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_v(); | ||
757 | else | ||
758 | mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_v(); | ||
759 | |||
760 | mmu_debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
761 | mmu_debug_ctrl = set_field(mmu_debug_ctrl, fb_mmu_debug_ctrl_debug_m(), mmu_debug_ctrl); | ||
762 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), mmu_debug_ctrl); | ||
763 | } | ||
764 | |||
765 | static int gk20a_pm_finalize_poweron(struct device *dev) | 750 | static int gk20a_pm_finalize_poweron(struct device *dev) |
766 | { | 751 | { |
767 | struct platform_device *pdev = to_platform_device(dev); | 752 | struct platform_device *pdev = to_platform_device(dev); |
@@ -890,7 +875,7 @@ static int gk20a_pm_finalize_poweron(struct device *dev) | |||
890 | } | 875 | } |
891 | 876 | ||
892 | /* Restore the debug setting */ | 877 | /* Restore the debug setting */ |
893 | gk20a_pm_restore_debug_setting(g); | 878 | g->ops.mm.set_debug_mode(g, g->mmu_debug_ctrl); |
894 | 879 | ||
895 | gk20a_channel_resume(g); | 880 | gk20a_channel_resume(g); |
896 | set_user_nice(current, nice_value); | 881 | set_user_nice(current, nice_value); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ff37039f..fe51f356 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -346,6 +346,7 @@ struct gpu_ops { | |||
346 | struct { | 346 | struct { |
347 | bool (*support_sparse)(struct gk20a *g); | 347 | bool (*support_sparse)(struct gk20a *g); |
348 | bool (*is_debug_mode_enabled)(struct gk20a *g); | 348 | bool (*is_debug_mode_enabled)(struct gk20a *g); |
349 | void (*set_debug_mode)(struct gk20a *g, bool enable); | ||
349 | u64 (*gmmu_map)(struct vm_gk20a *vm, | 350 | u64 (*gmmu_map)(struct vm_gk20a *vm, |
350 | u64 map_offset, | 351 | u64 map_offset, |
351 | struct sg_table *sgt, | 352 | struct sg_table *sgt, |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 86b9f045..4c31d5e4 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -3723,6 +3723,24 @@ bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g) | |||
3723 | fb_mmu_debug_ctrl_debug_enabled_v(); | 3723 | fb_mmu_debug_ctrl_debug_enabled_v(); |
3724 | } | 3724 | } |
3725 | 3725 | ||
3726 | static void gk20a_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) | ||
3727 | { | ||
3728 | u32 reg_val, debug_ctrl; | ||
3729 | |||
3730 | reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
3731 | if (enable) { | ||
3732 | debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); | ||
3733 | g->mmu_debug_ctrl = true; | ||
3734 | } else { | ||
3735 | debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); | ||
3736 | g->mmu_debug_ctrl = false; | ||
3737 | } | ||
3738 | |||
3739 | reg_val = set_field(reg_val, | ||
3740 | fb_mmu_debug_ctrl_debug_m(), debug_ctrl); | ||
3741 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | ||
3742 | } | ||
3743 | |||
3726 | u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g) | 3744 | u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g) |
3727 | { | 3745 | { |
3728 | return 34; | 3746 | return 34; |
@@ -3769,6 +3787,7 @@ clean_up: | |||
3769 | void gk20a_init_mm(struct gpu_ops *gops) | 3787 | void gk20a_init_mm(struct gpu_ops *gops) |
3770 | { | 3788 | { |
3771 | gops->mm.is_debug_mode_enabled = gk20a_mm_mmu_debug_mode_enabled; | 3789 | gops->mm.is_debug_mode_enabled = gk20a_mm_mmu_debug_mode_enabled; |
3790 | gops->mm.set_debug_mode = gk20a_mm_mmu_set_debug_mode; | ||
3772 | gops->mm.gmmu_map = gk20a_locked_gmmu_map; | 3791 | gops->mm.gmmu_map = gk20a_locked_gmmu_map; |
3773 | gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; | 3792 | gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; |
3774 | gops->mm.vm_remove = gk20a_vm_remove_support; | 3793 | gops->mm.vm_remove = gk20a_vm_remove_support; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index a941eb59..4a712394 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -3562,6 +3562,10 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) | |||
3562 | { | 3562 | { |
3563 | return 0x004188b0; | 3563 | return 0x004188b0; |
3564 | } | 3564 | } |
3565 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_m(void) | ||
3566 | { | ||
3567 | return 0x1 << 16; | ||
3568 | } | ||
3565 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) | 3569 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) |
3566 | { | 3570 | { |
3567 | return (r >> 16) & 0x1; | 3571 | return (r >> 16) & 0x1; |
@@ -3570,6 +3574,18 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) | |||
3570 | { | 3574 | { |
3571 | return 0x00000001; | 3575 | return 0x00000001; |
3572 | } | 3576 | } |
3577 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(void) | ||
3578 | { | ||
3579 | return 0x10000; | ||
3580 | } | ||
3581 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_v(void) | ||
3582 | { | ||
3583 | return 0x00000000; | ||
3584 | } | ||
3585 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(void) | ||
3586 | { | ||
3587 | return 0x0; | ||
3588 | } | ||
3573 | static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) | 3589 | static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) |
3574 | { | 3590 | { |
3575 | return 0x004188b4; | 3591 | return 0x004188b4; |
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index 3d75a631..9fdd860b 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c | |||
@@ -78,6 +78,31 @@ static bool gm20b_mm_mmu_debug_mode_enabled(struct gk20a *g) | |||
78 | gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(); | 78 | gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(); |
79 | } | 79 | } |
80 | 80 | ||
81 | static void gm20b_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) | ||
82 | { | ||
83 | u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl; | ||
84 | |||
85 | if (enable) { | ||
86 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); | ||
87 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(); | ||
88 | g->mmu_debug_ctrl = true; | ||
89 | } else { | ||
90 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); | ||
91 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(); | ||
92 | g->mmu_debug_ctrl = false; | ||
93 | } | ||
94 | |||
95 | reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
96 | reg_val = set_field(reg_val, | ||
97 | fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); | ||
98 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | ||
99 | |||
100 | reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | ||
101 | reg_val = set_field(reg_val, | ||
102 | gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); | ||
103 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); | ||
104 | } | ||
105 | |||
81 | static void gm20b_mm_set_big_page_size(struct gk20a *g, | 106 | static void gm20b_mm_set_big_page_size(struct gk20a *g, |
82 | void *inst_ptr, int size) | 107 | void *inst_ptr, int size) |
83 | { | 108 | { |
@@ -112,6 +137,7 @@ void gm20b_init_mm(struct gpu_ops *gops) | |||
112 | { | 137 | { |
113 | gops->mm.support_sparse = gm20b_mm_support_sparse; | 138 | gops->mm.support_sparse = gm20b_mm_support_sparse; |
114 | gops->mm.is_debug_mode_enabled = gm20b_mm_mmu_debug_mode_enabled; | 139 | gops->mm.is_debug_mode_enabled = gm20b_mm_mmu_debug_mode_enabled; |
140 | gops->mm.set_debug_mode = gm20b_mm_mmu_set_debug_mode; | ||
115 | gops->mm.gmmu_map = gk20a_locked_gmmu_map; | 141 | gops->mm.gmmu_map = gk20a_locked_gmmu_map; |
116 | gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; | 142 | gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; |
117 | gops->mm.vm_remove = gk20a_vm_remove_support; | 143 | gops->mm.vm_remove = gk20a_vm_remove_support; |