gpu: nvgpu: Mask an unused HCE_ILLEGAL_OP Interrupt

HCE interrupt is not being used in nvgpu platform now,
masking the bit from the interrupt register.

bug 2082123

Change-Id: I1d53584afebe57b9621c8f4ec395cd1dcd6c7611
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1746850
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

8 files changed, 59 insertions, 11 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 997856aa..00119300 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -834,11 +834,14 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
                 gk20a_writel(g, pbdma_intr_stall_r(i), intr_stall);
                 nvgpu_log_info(g, "pbdma id:%u, intr_en_0 0x%08x", i, intr_stall);
                 gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall);
-
-                nvgpu_log_info(g, "pbdma id:%u, intr_en_1 0x%08x", i,
-                                 ~pbdma_intr_en_0_lbreq_enabled_f());
-                gk20a_writel(g, pbdma_intr_en_1_r(i),
-                        ~pbdma_intr_en_0_lbreq_enabled_f());
+                intr_stall = gk20a_readl(g, pbdma_intr_stall_1_r(i));
+                /*
+                 * For bug 2082123
+                 * Mask the unused HCE_RE_ILLEGAL_OP bit from the interrupt.
+                 */
+                intr_stall &= ~pbdma_intr_stall_1_hce_illegal_op_enabled_f();
+                nvgpu_log_info(g, "pbdma id:%u, intr_en_1 0x%08x", i, intr_stall);
+                gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall);
         }
 
         /* reset runlist interrupts */
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index fdd9ecf0..a7c6360b 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -1222,6 +1222,11 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
                 gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall);
 
                 intr_stall = gk20a_readl(g, pbdma_intr_stall_1_r(i));
+                /*
+                 * For bug 2082123
+                 * Mask the unused HCE_RE_ILLEGAL_OP bit from the interrupt.
+                 */
+                intr_stall &= ~pbdma_intr_stall_1_hce_illegal_op_enabled_f();
                 nvgpu_log_info(g, "pbdma id:%u, intr_en_1 0x%08x", i, intr_stall);
                 gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall);
         }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h
index 338edef2..2c8f48d6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -528,6 +528,14 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
 {
         return 0x100U;
 }
+static inline u32 pbdma_intr_stall_1_r(u32 i)
+{
+        return 0x00040140U + i*8192U;
+}
+static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
+{
+        return 0x1U;
+}
 static inline u32 pbdma_udma_nop_r(void)
 {
         return 0x00000008U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
index b8d7bbe4..10ed9eca 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -516,6 +516,14 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
 {
         return 0x100U;
 }
+static inline u32 pbdma_intr_stall_1_r(u32 i)
+{
+        return 0x00040140U + i*8192U;
+}
+static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
+{
+        return 0x1U;
+}
 static inline u32 pbdma_udma_nop_r(void)
 {
         return 0x00000008U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h
index dad6317d..1005c5ab 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -504,6 +504,14 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
 {
         return 0x100U;
 }
+static inline u32 pbdma_intr_stall_1_r(u32 i)
+{
+        return 0x00040140U + i*8192U;
+}
+static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
+{
+        return 0x1U;
+}
 static inline u32 pbdma_udma_nop_r(void)
 {
         return 0x00000008U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
index 4f45f824..66e8ddbf 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -528,6 +528,14 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
 {
         return 0x100U;
 }
+static inline u32 pbdma_intr_stall_1_r(u32 i)
+{
+        return 0x00040140U + i*8192U;
+}
+static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
+{
+        return 0x1U;
+}
 static inline u32 pbdma_udma_nop_r(void)
 {
         return 0x00000008U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
index 4b7eb25c..a5c8dad3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -548,6 +548,10 @@ static inline u32 pbdma_intr_stall_1_r(u32 i)
 {
         return 0x00040140U + i*8192U;
 }
+static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
+{
+        return 0x1U;
+}
 static inline u32 pbdma_udma_nop_r(void)
 {
         return 0x00000008U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h
index f05bee84..75bdae1c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -548,6 +548,10 @@ static inline u32 pbdma_intr_stall_1_r(u32 i)
 {
         return 0x00040140U + i*8192U;
 }
+static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
+{
+        return 0x1U;
+}
 static inline u32 pbdma_udma_nop_r(void)
 {
         return 0x00000008U;