diff options
author | Amulya <Amurthyreddy@nvidia.com> | 2018-08-14 01:00:46 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-28 13:33:52 -0400 |
commit | 06f54be8c979720515d22e24cb4a20868af45f59 (patch) | |
tree | ac7ae4b02ef859586170b33d0106910c9f3e8b2b /drivers/gpu | |
parent | 361eca66b58051d46daad1b600eef1f72b7f15c0 (diff) |
gpu: nvgpu: Fix MISRA 10.1-Using boolean as a bit
Fix violations where a boolean is used as an operand in bit-shift
operations and is interpreted as a numerical value.
JIRA NVGPU-649
Change-Id: I4494c3b69d0e53319331b47d0a4de0b3de279f4f
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1799322
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
8 files changed, 84 insertions, 47 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index 92f88333..e6e16511 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | |||
@@ -361,11 +361,11 @@ static int gk20a_flcn_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, | |||
361 | words, dst, blk, tag); | 361 | words, dst, blk, tag); |
362 | 362 | ||
363 | gk20a_writel(g, base_addr + falcon_falcon_imemc_r(port), | 363 | gk20a_writel(g, base_addr + falcon_falcon_imemc_r(port), |
364 | falcon_falcon_imemc_offs_f(dst >> 2) | | 364 | falcon_falcon_imemc_offs_f(dst >> 2) | |
365 | falcon_falcon_imemc_blk_f(blk) | | 365 | falcon_falcon_imemc_blk_f(blk) | |
366 | /* Set Auto-Increment on write */ | 366 | /* Set Auto-Increment on write */ |
367 | falcon_falcon_imemc_aincw_f(1) | | 367 | falcon_falcon_imemc_aincw_f(1) | |
368 | sec << 28); | 368 | falcon_falcon_imemc_secure_f(sec ? 1U : 0U)); |
369 | 369 | ||
370 | for (i = 0; i < words; i++) { | 370 | for (i = 0; i < words; i++) { |
371 | if (i % 64 == 0) { | 371 | if (i % 64 == 0) { |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index bc659a7b..8b3253a1 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <nvgpu/soc.h> | 34 | #include <nvgpu/soc.h> |
35 | #include <nvgpu/io.h> | 35 | #include <nvgpu/io.h> |
36 | #include <nvgpu/utils.h> | 36 | #include <nvgpu/utils.h> |
37 | #include <nvgpu/bitops.h> | ||
37 | 38 | ||
38 | #include "gk20a/gk20a.h" | 39 | #include "gk20a/gk20a.h" |
39 | #include "gk20a/gr_gk20a.h" | 40 | #include "gk20a/gr_gk20a.h" |
@@ -235,9 +236,10 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
235 | l1_tag_ecc_corrected_err_status, is_l1_tag_ecc_corrected_total_err_overflow); | 236 | l1_tag_ecc_corrected_err_status, is_l1_tag_ecc_corrected_total_err_overflow); |
236 | 237 | ||
237 | /* HW uses 16-bits counter */ | 238 | /* HW uses 16-bits counter */ |
238 | l1_tag_corrected_err_count_delta += | 239 | if (is_l1_tag_ecc_corrected_total_err_overflow) { |
239 | (is_l1_tag_ecc_corrected_total_err_overflow << | 240 | l1_tag_corrected_err_count_delta += |
240 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s()); | 241 | BIT32(gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s()); |
242 | } | ||
241 | g->ecc.gr.sm_l1_tag_ecc_corrected_err_count[gpc][tpc].counter += | 243 | g->ecc.gr.sm_l1_tag_ecc_corrected_err_count[gpc][tpc].counter += |
242 | l1_tag_corrected_err_count_delta; | 244 | l1_tag_corrected_err_count_delta; |
243 | gk20a_writel(g, | 245 | gk20a_writel(g, |
@@ -250,9 +252,10 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
250 | l1_tag_ecc_uncorrected_err_status, is_l1_tag_ecc_uncorrected_total_err_overflow); | 252 | l1_tag_ecc_uncorrected_err_status, is_l1_tag_ecc_uncorrected_total_err_overflow); |
251 | 253 | ||
252 | /* HW uses 16-bits counter */ | 254 | /* HW uses 16-bits counter */ |
253 | l1_tag_uncorrected_err_count_delta += | 255 | if (is_l1_tag_ecc_uncorrected_total_err_overflow) { |
254 | (is_l1_tag_ecc_uncorrected_total_err_overflow << | 256 | l1_tag_uncorrected_err_count_delta += |
255 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s()); | 257 | BIT32(gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s()); |
258 | } | ||
256 | g->ecc.gr.sm_l1_tag_ecc_uncorrected_err_count[gpc][tpc].counter += | 259 | g->ecc.gr.sm_l1_tag_ecc_uncorrected_err_count[gpc][tpc].counter += |
257 | l1_tag_uncorrected_err_count_delta; | 260 | l1_tag_uncorrected_err_count_delta; |
258 | gk20a_writel(g, | 261 | gk20a_writel(g, |
@@ -328,9 +331,10 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
328 | lrf_ecc_corrected_err_status, is_lrf_ecc_corrected_total_err_overflow); | 331 | lrf_ecc_corrected_err_status, is_lrf_ecc_corrected_total_err_overflow); |
329 | 332 | ||
330 | /* HW uses 16-bits counter */ | 333 | /* HW uses 16-bits counter */ |
331 | lrf_corrected_err_count_delta += | 334 | if (is_lrf_ecc_corrected_total_err_overflow) { |
332 | (is_lrf_ecc_corrected_total_err_overflow << | 335 | lrf_corrected_err_count_delta += |
333 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s()); | 336 | BIT32(gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s()); |
337 | } | ||
334 | g->ecc.gr.sm_lrf_ecc_single_err_count[gpc][tpc].counter += | 338 | g->ecc.gr.sm_lrf_ecc_single_err_count[gpc][tpc].counter += |
335 | lrf_corrected_err_count_delta; | 339 | lrf_corrected_err_count_delta; |
336 | gk20a_writel(g, | 340 | gk20a_writel(g, |
@@ -343,9 +347,10 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
343 | lrf_ecc_uncorrected_err_status, is_lrf_ecc_uncorrected_total_err_overflow); | 347 | lrf_ecc_uncorrected_err_status, is_lrf_ecc_uncorrected_total_err_overflow); |
344 | 348 | ||
345 | /* HW uses 16-bits counter */ | 349 | /* HW uses 16-bits counter */ |
346 | lrf_uncorrected_err_count_delta += | 350 | if (is_lrf_ecc_uncorrected_total_err_overflow) { |
347 | (is_lrf_ecc_uncorrected_total_err_overflow << | 351 | lrf_uncorrected_err_count_delta += |
348 | gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s()); | 352 | BIT32(gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s()); |
353 | } | ||
349 | g->ecc.gr.sm_lrf_ecc_double_err_count[gpc][tpc].counter += | 354 | g->ecc.gr.sm_lrf_ecc_double_err_count[gpc][tpc].counter += |
350 | lrf_uncorrected_err_count_delta; | 355 | lrf_uncorrected_err_count_delta; |
351 | gk20a_writel(g, | 356 | gk20a_writel(g, |
@@ -488,9 +493,10 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
488 | cbu_ecc_corrected_err_status, is_cbu_ecc_corrected_total_err_overflow); | 493 | cbu_ecc_corrected_err_status, is_cbu_ecc_corrected_total_err_overflow); |
489 | 494 | ||
490 | /* HW uses 16-bits counter */ | 495 | /* HW uses 16-bits counter */ |
491 | cbu_corrected_err_count_delta += | 496 | if (is_cbu_ecc_corrected_total_err_overflow) { |
492 | (is_cbu_ecc_corrected_total_err_overflow << | 497 | cbu_corrected_err_count_delta += |
493 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s()); | 498 | BIT32(gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s()); |
499 | } | ||
494 | g->ecc.gr.sm_cbu_ecc_corrected_err_count[gpc][tpc].counter += | 500 | g->ecc.gr.sm_cbu_ecc_corrected_err_count[gpc][tpc].counter += |
495 | cbu_corrected_err_count_delta; | 501 | cbu_corrected_err_count_delta; |
496 | gk20a_writel(g, | 502 | gk20a_writel(g, |
@@ -503,9 +509,10 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
503 | cbu_ecc_uncorrected_err_status, is_cbu_ecc_uncorrected_total_err_overflow); | 509 | cbu_ecc_uncorrected_err_status, is_cbu_ecc_uncorrected_total_err_overflow); |
504 | 510 | ||
505 | /* HW uses 16-bits counter */ | 511 | /* HW uses 16-bits counter */ |
506 | cbu_uncorrected_err_count_delta += | 512 | if (is_cbu_ecc_uncorrected_total_err_overflow) { |
507 | (is_cbu_ecc_uncorrected_total_err_overflow << | 513 | cbu_uncorrected_err_count_delta += |
508 | gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()); | 514 | BIT32(gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()); |
515 | } | ||
509 | g->ecc.gr.sm_cbu_ecc_uncorrected_err_count[gpc][tpc].counter += | 516 | g->ecc.gr.sm_cbu_ecc_uncorrected_err_count[gpc][tpc].counter += |
510 | cbu_uncorrected_err_count_delta; | 517 | cbu_uncorrected_err_count_delta; |
511 | gk20a_writel(g, | 518 | gk20a_writel(g, |
@@ -569,9 +576,10 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
569 | l1_data_ecc_corrected_err_status, is_l1_data_ecc_corrected_total_err_overflow); | 576 | l1_data_ecc_corrected_err_status, is_l1_data_ecc_corrected_total_err_overflow); |
570 | 577 | ||
571 | /* HW uses 16-bits counter */ | 578 | /* HW uses 16-bits counter */ |
572 | l1_data_corrected_err_count_delta += | 579 | if (is_l1_data_ecc_corrected_total_err_overflow) { |
573 | (is_l1_data_ecc_corrected_total_err_overflow << | 580 | l1_data_corrected_err_count_delta += |
574 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s()); | 581 | BIT32(gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s()); |
582 | } | ||
575 | g->ecc.gr.sm_l1_data_ecc_corrected_err_count[gpc][tpc].counter += | 583 | g->ecc.gr.sm_l1_data_ecc_corrected_err_count[gpc][tpc].counter += |
576 | l1_data_corrected_err_count_delta; | 584 | l1_data_corrected_err_count_delta; |
577 | gk20a_writel(g, | 585 | gk20a_writel(g, |
@@ -584,9 +592,10 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
584 | l1_data_ecc_uncorrected_err_status, is_l1_data_ecc_uncorrected_total_err_overflow); | 592 | l1_data_ecc_uncorrected_err_status, is_l1_data_ecc_uncorrected_total_err_overflow); |
585 | 593 | ||
586 | /* HW uses 16-bits counter */ | 594 | /* HW uses 16-bits counter */ |
587 | l1_data_uncorrected_err_count_delta += | 595 | if (is_l1_data_ecc_uncorrected_total_err_overflow) { |
588 | (is_l1_data_ecc_uncorrected_total_err_overflow << | 596 | l1_data_uncorrected_err_count_delta += |
589 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()); | 597 | BIT32(gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()); |
598 | } | ||
590 | g->ecc.gr.sm_l1_data_ecc_uncorrected_err_count[gpc][tpc].counter += | 599 | g->ecc.gr.sm_l1_data_ecc_uncorrected_err_count[gpc][tpc].counter += |
591 | l1_data_uncorrected_err_count_delta; | 600 | l1_data_uncorrected_err_count_delta; |
592 | gk20a_writel(g, | 601 | gk20a_writel(g, |
@@ -654,9 +663,10 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
654 | icache_ecc_corrected_err_status, is_icache_ecc_corrected_total_err_overflow); | 663 | icache_ecc_corrected_err_status, is_icache_ecc_corrected_total_err_overflow); |
655 | 664 | ||
656 | /* HW uses 16-bits counter */ | 665 | /* HW uses 16-bits counter */ |
657 | icache_corrected_err_count_delta += | 666 | if (is_icache_ecc_corrected_total_err_overflow) { |
658 | (is_icache_ecc_corrected_total_err_overflow << | 667 | icache_corrected_err_count_delta += |
659 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()); | 668 | BIT32(gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()); |
669 | } | ||
660 | g->ecc.gr.sm_icache_ecc_corrected_err_count[gpc][tpc].counter += | 670 | g->ecc.gr.sm_icache_ecc_corrected_err_count[gpc][tpc].counter += |
661 | icache_corrected_err_count_delta; | 671 | icache_corrected_err_count_delta; |
662 | gk20a_writel(g, | 672 | gk20a_writel(g, |
@@ -669,9 +679,10 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
669 | icache_ecc_uncorrected_err_status, is_icache_ecc_uncorrected_total_err_overflow); | 679 | icache_ecc_uncorrected_err_status, is_icache_ecc_uncorrected_total_err_overflow); |
670 | 680 | ||
671 | /* HW uses 16-bits counter */ | 681 | /* HW uses 16-bits counter */ |
672 | icache_uncorrected_err_count_delta += | 682 | if (is_icache_ecc_uncorrected_total_err_overflow) { |
673 | (is_icache_ecc_uncorrected_total_err_overflow << | 683 | icache_uncorrected_err_count_delta += |
674 | gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()); | 684 | BIT32(gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()); |
685 | } | ||
675 | g->ecc.gr.sm_icache_ecc_uncorrected_err_count[gpc][tpc].counter += | 686 | g->ecc.gr.sm_icache_ecc_uncorrected_err_count[gpc][tpc].counter += |
676 | icache_uncorrected_err_count_delta; | 687 | icache_uncorrected_err_count_delta; |
677 | gk20a_writel(g, | 688 | gk20a_writel(g, |
@@ -759,9 +770,10 @@ int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
759 | gcc_l15_ecc_corrected_err_status, is_gcc_l15_ecc_corrected_total_err_overflow); | 770 | gcc_l15_ecc_corrected_err_status, is_gcc_l15_ecc_corrected_total_err_overflow); |
760 | 771 | ||
761 | /* HW uses 16-bits counter */ | 772 | /* HW uses 16-bits counter */ |
762 | gcc_l15_corrected_err_count_delta += | 773 | if (is_gcc_l15_ecc_corrected_total_err_overflow) { |
763 | (is_gcc_l15_ecc_corrected_total_err_overflow << | 774 | gcc_l15_corrected_err_count_delta += |
764 | gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s()); | 775 | BIT32(gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s()); |
776 | } | ||
765 | g->ecc.gr.gcc_l15_ecc_corrected_err_count[gpc].counter += | 777 | g->ecc.gr.gcc_l15_ecc_corrected_err_count[gpc].counter += |
766 | gcc_l15_corrected_err_count_delta; | 778 | gcc_l15_corrected_err_count_delta; |
767 | gk20a_writel(g, | 779 | gk20a_writel(g, |
@@ -774,9 +786,10 @@ int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
774 | gcc_l15_ecc_uncorrected_err_status, is_gcc_l15_ecc_uncorrected_total_err_overflow); | 786 | gcc_l15_ecc_uncorrected_err_status, is_gcc_l15_ecc_uncorrected_total_err_overflow); |
775 | 787 | ||
776 | /* HW uses 16-bits counter */ | 788 | /* HW uses 16-bits counter */ |
777 | gcc_l15_uncorrected_err_count_delta += | 789 | if (is_gcc_l15_ecc_uncorrected_total_err_overflow) { |
778 | (is_gcc_l15_ecc_uncorrected_total_err_overflow << | 790 | gcc_l15_uncorrected_err_count_delta += |
779 | gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s()); | 791 | BIT32(gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s()); |
792 | } | ||
780 | g->ecc.gr.gcc_l15_ecc_uncorrected_err_count[gpc].counter += | 793 | g->ecc.gr.gcc_l15_ecc_uncorrected_err_count[gpc].counter += |
781 | gcc_l15_uncorrected_err_count_delta; | 794 | gcc_l15_uncorrected_err_count_delta; |
782 | gk20a_writel(g, | 795 | gk20a_writel(g, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h index 27fb5884..7b4d87b0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -336,6 +336,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) | |||
336 | { | 336 | { |
337 | return (v & 0x1U) << 24U; | 337 | return (v & 0x1U) << 24U; |
338 | } | 338 | } |
339 | static inline u32 falcon_falcon_imemc_secure_f(u32 v) | ||
340 | { | ||
341 | return (v & 0x1U) << 28U; | ||
342 | } | ||
339 | static inline u32 falcon_falcon_imemd_r(u32 i) | 343 | static inline u32 falcon_falcon_imemd_r(u32 i) |
340 | { | 344 | { |
341 | return 0x00000184U + i*16U; | 345 | return 0x00000184U + i*16U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h index a17c9a9a..c5985685 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -356,6 +356,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) | |||
356 | { | 356 | { |
357 | return (v & 0x1U) << 24U; | 357 | return (v & 0x1U) << 24U; |
358 | } | 358 | } |
359 | static inline u32 falcon_falcon_imemc_secure_f(u32 v) | ||
360 | { | ||
361 | return (v & 0x1U) << 28U; | ||
362 | } | ||
359 | static inline u32 falcon_falcon_imemd_r(u32 i) | 363 | static inline u32 falcon_falcon_imemd_r(u32 i) |
360 | { | 364 | { |
361 | return 0x00000184U + i*16U; | 365 | return 0x00000184U + i*16U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h index 6740b2a6..d899e3f3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -356,6 +356,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) | |||
356 | { | 356 | { |
357 | return (v & 0x1U) << 24U; | 357 | return (v & 0x1U) << 24U; |
358 | } | 358 | } |
359 | static inline u32 falcon_falcon_imemc_secure_f(u32 v) | ||
360 | { | ||
361 | return (v & 0x1U) << 28U; | ||
362 | } | ||
359 | static inline u32 falcon_falcon_imemd_r(u32 i) | 363 | static inline u32 falcon_falcon_imemd_r(u32 i) |
360 | { | 364 | { |
361 | return 0x00000184U + i*16U; | 365 | return 0x00000184U + i*16U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h index 918f262b..6dc401d6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -356,6 +356,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) | |||
356 | { | 356 | { |
357 | return (v & 0x1U) << 24U; | 357 | return (v & 0x1U) << 24U; |
358 | } | 358 | } |
359 | static inline u32 falcon_falcon_imemc_secure_f(u32 v) | ||
360 | { | ||
361 | return (v & 0x1U) << 28U; | ||
362 | } | ||
359 | static inline u32 falcon_falcon_imemd_r(u32 i) | 363 | static inline u32 falcon_falcon_imemd_r(u32 i) |
360 | { | 364 | { |
361 | return 0x00000184U + i*16U; | 365 | return 0x00000184U + i*16U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h index 122956bb..3492d68c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -356,6 +356,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) | |||
356 | { | 356 | { |
357 | return (v & 0x1U) << 24U; | 357 | return (v & 0x1U) << 24U; |
358 | } | 358 | } |
359 | static inline u32 falcon_falcon_imemc_secure_f(u32 v) | ||
360 | { | ||
361 | return (v & 0x1U) << 28U; | ||
362 | } | ||
359 | static inline u32 falcon_falcon_imemd_r(u32 i) | 363 | static inline u32 falcon_falcon_imemd_r(u32 i) |
360 | { | 364 | { |
361 | return 0x00000184U + i*16U; | 365 | return 0x00000184U + i*16U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index 4bb8f2de..31e883e5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -356,6 +356,10 @@ static inline u32 falcon_falcon_imemc_aincw_f(u32 v) | |||
356 | { | 356 | { |
357 | return (v & 0x1U) << 24U; | 357 | return (v & 0x1U) << 24U; |
358 | } | 358 | } |
359 | static inline u32 falcon_falcon_imemc_secure_f(u32 v) | ||
360 | { | ||
361 | return (v & 0x1U) << 28U; | ||
362 | } | ||
359 | static inline u32 falcon_falcon_imemd_r(u32 i) | 363 | static inline u32 falcon_falcon_imemd_r(u32 i) |
360 | { | 364 | { |
361 | return 0x00000184U + i*16U; | 365 | return 0x00000184U + i*16U; |