gpu: nvgpu: Disable rd_coalesce for all chips

Disable read coalescing for all chips.

Bug 200314091

Change-Id: Iaa3f58f94369ae1edae0620083eca4594be730fd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1518308
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 23 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 58558159..4878fdd6 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -408,6 +408,7 @@ struct gpu_ops {
                 void (*resume_single_sm)(struct gk20a *g,
                                 u32 gpc, u32 tpc, u32 sm);
                 void (*resume_all_sms)(struct gk20a *g);
+                void (*disable_rd_coalesce)(struct gk20a *g);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 608b011a..cd1d31a5 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4521,6 +4521,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
         if (g->ops.fb.init_cbc)
                 g->ops.fb.init_cbc(g, gr);
 
+        if (g->ops.gr.disable_rd_coalesce)
+                g->ops.gr.disable_rd_coalesce(g);
+
         /* load ctx init */
         for (i = 0; i < sw_ctx_load->count; i++)
                 gk20a_writel(g, sw_ctx_load->l[i].addr,
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 87cf3f01..56ebc8ca 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1542,6 +1542,24 @@ static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
         gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0);
 }
 
+/*
+ * Disable both surface and LG coalesce.
+ */
+void gm20a_gr_disable_rd_coalesce(struct gk20a *g)
+{
+        u32 dbg2_reg;
+
+        dbg2_reg = gk20a_readl(g, gr_gpcs_tpcs_tex_m_dbg2_r());
+        dbg2_reg = set_field(dbg2_reg,
+                             gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(),
+                             gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(0));
+        dbg2_reg = set_field(dbg2_reg,
+                             gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(),
+                             gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(0));
+
+        gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), dbg2_reg);
+}
+
 void gm20b_init_gr(struct gk20a *g)
 {
         struct gpu_ops *gops = &g->ops;
@@ -1657,4 +1675,5 @@ void gm20b_init_gr(struct gk20a *g)
         gops->gr.clear_sm_hww = gm20b_gr_clear_sm_hww;
         gops->gr.init_ovr_sm_dsm_perf =  gk20a_gr_init_ovr_sm_dsm_perf;
         gops->gr.get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs;
+        gops->gr.disable_rd_coalesce = gm20a_gr_disable_rd_coalesce;
 }