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authorSeema Khowala <seemaj@nvidia.com>2018-03-27 01:31:56 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-29 16:53:50 -0400
commitf81d83690f9d08be0daf8a488331fb04d9d23c46 (patch)
tree1590155c199a62cfd8811297c3d656d0733a5df4 /drivers/gpu/nvgpu
parent8a64eea483d18ce603b049d5485e9f7a742da30b (diff)
gpu: nvgpu: use gpc_tpc_count[gpc] for number of tpc in a gpc
Using tpc_count instead of gpc_tpc_count indexed by gpc, will result in pbus error with decode error or client floorswept error codes. tpc_count represents total number of tpc while gpc_tpc_count[gpc] represents number of tpc in the indexed gpc. Bug 1998067 Change-Id: I9adfb98a6c3e209cbb02a8cd5090f6b6adc1ec4b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1682469 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c6
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c7
2 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 9d85a5ef..cf63546b 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4417,7 +4417,7 @@ void gk20a_gr_enable_gpc_exceptions(struct gk20a *g)
4417 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); 4417 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f());
4418 4418
4419 tpc_mask = 4419 tpc_mask =
4420 gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); 4420 gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->max_tpc_per_gpc_count) - 1);
4421 4421
4422 gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), tpc_mask); 4422 gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), tpc_mask);
4423} 4423}
@@ -5792,7 +5792,7 @@ static int gk20a_gr_handle_gpc_exception(struct gk20a *g, bool *post_event,
5792 + gpc_offset); 5792 + gpc_offset);
5793 5793
5794 /* check if any tpc has an exception */ 5794 /* check if any tpc has an exception */
5795 for (tpc = 0; tpc < gr->tpc_count; tpc++) { 5795 for (tpc = 0; tpc < gr->gpc_tpc_count[gpc]; tpc++) {
5796 if ((gr_gpc0_gpccs_gpc_exception_tpc_v(gpc_exception) & 5796 if ((gr_gpc0_gpccs_gpc_exception_tpc_v(gpc_exception) &
5797 (1 << tpc)) == 0) 5797 (1 << tpc)) == 0)
5798 continue; 5798 continue;
@@ -8674,7 +8674,7 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g)
8674 for (gpc = 0; gpc < gr->gpc_count; gpc++) { 8674 for (gpc = 0; gpc < gr->gpc_count; gpc++) {
8675 8675
8676 /* check if any tpc has an exception */ 8676 /* check if any tpc has an exception */
8677 for (tpc = 0; tpc < gr->tpc_count; tpc++) { 8677 for (tpc = 0; tpc < gr->gpc_tpc_count[gpc]; tpc++) {
8678 8678
8679 for (sm = 0; sm < sm_per_tpc; sm++) { 8679 for (sm = 0; sm < sm_per_tpc; sm++) {
8680 global_esr = g->ops.gr.get_sm_hww_global_esr(g, 8680 global_esr = g->ops.gr.get_sm_hww_global_esr(g,
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 4f517fa7..e0c60efb 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -939,7 +939,8 @@ void gr_gv11b_enable_gpc_exceptions(struct gk20a *g)
939 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f()); 939 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f());
940 940
941 tpc_mask = 941 tpc_mask =
942 gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); 942 gr_gpcs_gpccs_gpc_exception_en_tpc_f(
943 (1 << gr->max_tpc_per_gpc_count) - 1);
943 944
944 gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), 945 gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(),
945 (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) | 946 (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) |
@@ -1743,7 +1744,7 @@ static int gr_gv11b_dump_gr_sm_regs(struct gk20a *g,
1743 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { 1744 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
1744 gpc_offset = gk20a_gr_gpc_offset(g, gpc); 1745 gpc_offset = gk20a_gr_gpc_offset(g, gpc);
1745 1746
1746 for (tpc = 0; tpc < g->gr.tpc_count; tpc++) { 1747 for (tpc = 0; tpc < g->gr.gpc_tpc_count[gpc]; tpc++) {
1747 tpc_offset = gk20a_gr_tpc_offset(g, tpc); 1748 tpc_offset = gk20a_gr_tpc_offset(g, tpc);
1748 1749
1749 for (sm = 0; sm < sm_per_tpc; sm++) { 1750 for (sm = 0; sm < sm_per_tpc; sm++) {
@@ -4155,7 +4156,7 @@ static int gr_gv11b_ecc_scrub_is_done(struct gk20a *g,
4155 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { 4156 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
4156 gpc_offset = gk20a_gr_gpc_offset(g, gpc); 4157 gpc_offset = gk20a_gr_gpc_offset(g, gpc);
4157 4158
4158 for (tpc = 0; tpc < g->gr.tpc_count; tpc++) { 4159 for (tpc = 0; tpc < g->gr.gpc_tpc_count[gpc]; tpc++) {
4159 tpc_offset = gk20a_gr_tpc_offset(g, tpc); 4160 tpc_offset = gk20a_gr_tpc_offset(g, tpc);
4160 4161
4161 do { 4162 do {