gpu: nvgpu: CONFIG_TEGRA_ACR is supported by default

TEGRA_ACR config is supposed to be enabled maxwell
onwards. Since gk20a support is no longer supported,
delete code that is not under TEGRA_ACR config

Change-Id: Id52485680bca1ceaadcb94f9603c0898c2002e02
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595437
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 0 insertions, 79 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
index 1a2d378a..b9d3f734 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
@@ -508,7 +508,6 @@ int vgpu_gm20b_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
 
-#ifdef CONFIG_TEGRA_ACR
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
                 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
         } else {
@@ -520,21 +519,6 @@ int vgpu_gm20b_init_hal(struct gk20a *g)
                         __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
                 }
         }
-#else
-        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-                gk20a_dbg_info("running ASIM with PRIV security disabled");
-                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-        } else {
-                val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
-                if (!val) {
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-                } else {
-                        gk20a_dbg_info("priv security is not supported but enabled");
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-                        return -EPERM;
-                }
-        }
-#endif
 
         /* priv security dependent ops */
         if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
index 6806b318..78f88d4d 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -539,7 +539,6 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
 
-#ifdef CONFIG_TEGRA_ACR
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
                 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
                 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
@@ -557,24 +556,6 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
                         __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
                 }
         }
-#else
-        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-                gk20a_dbg_info("running simulator with PRIV security disabled");
-                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-                __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
-        } else {
-                val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
-                if (val) {
-                        gk20a_dbg_info("priv security is not supported but enabled");
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-                        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
-                        return -EPERM;
-                } else {
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-                        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
-                }
-        }
-#endif
 
         /* priv security dependent ops */
         if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index ef46c1ee..0d032be0 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -737,7 +737,6 @@ u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr)
         return 0;
 }
 
-#ifdef CONFIG_TEGRA_ACR
 static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g)
 {
         struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info;
@@ -830,14 +829,6 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
 
         return 0;
 }
-#else
-
-int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
-{
-        return -EPERM;
-}
-
-#endif
 
 void gr_gm20b_detect_sm_arch(struct gk20a *g)
 {
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 227b6b6c..bb18d2d7 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -634,7 +634,6 @@ int gm20b_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
 
-#ifdef CONFIG_TEGRA_ACR
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
                 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
         } else {
@@ -646,21 +645,6 @@ int gm20b_init_hal(struct gk20a *g)
                         __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
                 }
         }
-#else
-        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-                gk20a_dbg_info("running ASIM with PRIV security disabled");
-                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-        } else {
-                val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
-                if (!val) {
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-                } else {
-                        gk20a_dbg_info("priv security is not supported but enabled");
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-                        return -EPERM;
-                }
-        }
-#endif
 
         /* priv security dependent ops */
         if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 9b3d1a2c..0b2a5712 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -662,7 +662,6 @@ int gp10b_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
 
-#ifdef CONFIG_TEGRA_ACR
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
                 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
                 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
@@ -680,24 +679,6 @@ int gp10b_init_hal(struct gk20a *g)
                         __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
                 }
         }
-#else
-        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-                gk20a_dbg_info("running simulator with PRIV security disabled");
-                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-                __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
-        } else {
-                val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
-                if (val) {
-                        gk20a_dbg_info("priv security is not supported but enabled");
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-                        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
-                        return -EPERM;
-                } else {
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-                        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
-                }
-        }
-#endif
 
         /* priv security dependent ops */
         if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {