diff options
author | Alex Waterman <alexw@nvidia.com> | 2017-08-16 19:19:53 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-04 05:21:47 -0400 |
commit | edb116661348f1bc843849cdcc318fa47cf9724a (patch) | |
tree | 61d978a3518a51bdb82e2d3681abf5fc9c75821e /drivers/gpu/nvgpu | |
parent | 2559fa295d0c478466e47496174fa2108ab01c33 (diff) |
gpu: nvgpu: rename ops.mm.get_physical_addr_bits
Rename get_physical_addr_bits and related functions to something that
more clearly conveys what they are doing. The basic idea of these
functions is to translate from a physical GPU address to a IOMMU GPU
address. To do that a particular bit (that varies from chip to chip)
is added to the physical address.
JIRA NVGPU-68
Change-Id: I536cc595c4397aad69a24f740bc74db03f52bc0a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1542966
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/nvgpu_mem.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/nvgpu_mem.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/mm_vgpu.c | 2 |
12 files changed, 25 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c b/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c index 8cf3011e..0be41a44 100644 --- a/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c +++ b/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c | |||
@@ -268,7 +268,7 @@ u64 nvgpu_mem_get_addr_sgl(struct gk20a *g, struct scatterlist *sgl) | |||
268 | if (sg_dma_address(sgl) == DMA_ERROR_CODE) | 268 | if (sg_dma_address(sgl) == DMA_ERROR_CODE) |
269 | return 0; | 269 | return 0; |
270 | 270 | ||
271 | return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl)); | 271 | return nvgpu_mem_iommu_translate(g, sg_dma_address(sgl)); |
272 | } | 272 | } |
273 | 273 | ||
274 | /* | 274 | /* |
@@ -452,8 +452,8 @@ static u64 nvgpu_mem_linux_sgl_gpu_addr(struct gk20a *g, void *sgl, | |||
452 | if (sg_dma_address((struct scatterlist *)sgl) == DMA_ERROR_CODE) | 452 | if (sg_dma_address((struct scatterlist *)sgl) == DMA_ERROR_CODE) |
453 | return 0; | 453 | return 0; |
454 | 454 | ||
455 | return gk20a_mm_smmu_vaddr_translate(g, | 455 | return nvgpu_mem_iommu_translate(g, |
456 | sg_dma_address((struct scatterlist *)sgl)); | 456 | sg_dma_address((struct scatterlist *)sgl)); |
457 | } | 457 | } |
458 | 458 | ||
459 | static void nvgpu_mem_linux_sgl_free(struct gk20a *g, struct nvgpu_sgt *sgt) | 459 | static void nvgpu_mem_linux_sgl_free(struct gk20a *g, struct nvgpu_sgt *sgt) |
diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c index 52d20883..faee482d 100644 --- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c +++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c | |||
@@ -22,6 +22,7 @@ | |||
22 | 22 | ||
23 | #include <nvgpu/kmem.h> | 23 | #include <nvgpu/kmem.h> |
24 | #include <nvgpu/nvgpu_mem.h> | 24 | #include <nvgpu/nvgpu_mem.h> |
25 | #include <nvgpu/dma.h> | ||
25 | 26 | ||
26 | #include "gk20a/gk20a.h" | 27 | #include "gk20a/gk20a.h" |
27 | 28 | ||
@@ -56,3 +57,14 @@ void nvgpu_sgt_free(struct nvgpu_sgt *sgt, struct gk20a *g) | |||
56 | if (sgt && sgt->ops->sgt_free) | 57 | if (sgt && sgt->ops->sgt_free) |
57 | sgt->ops->sgt_free(g, sgt); | 58 | sgt->ops->sgt_free(g, sgt); |
58 | } | 59 | } |
60 | |||
61 | u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys) | ||
62 | { | ||
63 | /* ensure it is not vidmem allocation */ | ||
64 | WARN_ON(is_vidmem_page_alloc(phys)); | ||
65 | |||
66 | if (nvgpu_iommuable(g) && g->ops.mm.get_iommu_bit) | ||
67 | return phys | 1ULL << g->ops.mm.get_iommu_bit(g); | ||
68 | |||
69 | return phys; | ||
70 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8dabee63..db38fae4 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -741,7 +741,7 @@ struct gpu_ops { | |||
741 | struct nvgpu_mem *mem, int size); | 741 | struct nvgpu_mem *mem, int size); |
742 | u32 (*get_big_page_sizes)(void); | 742 | u32 (*get_big_page_sizes)(void); |
743 | u32 (*get_default_big_page_size)(void); | 743 | u32 (*get_default_big_page_size)(void); |
744 | u32 (*get_physical_addr_bits)(struct gk20a *g); | 744 | u32 (*get_iommu_bit)(struct gk20a *g); |
745 | int (*init_mm_setup_hw)(struct gk20a *g); | 745 | int (*init_mm_setup_hw)(struct gk20a *g); |
746 | bool (*is_bar1_supported)(struct gk20a *g); | 746 | bool (*is_bar1_supported)(struct gk20a *g); |
747 | int (*init_bar2_vm)(struct gk20a *g); | 747 | int (*init_bar2_vm)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 3d1f8d28..795f7bda 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -1271,17 +1271,6 @@ dma_addr_t gk20a_mm_gpuva_to_iova_base(struct vm_gk20a *vm, u64 gpu_vaddr) | |||
1271 | return addr; | 1271 | return addr; |
1272 | } | 1272 | } |
1273 | 1273 | ||
1274 | u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, u64 iova) | ||
1275 | { | ||
1276 | /* ensure it is not vidmem allocation */ | ||
1277 | WARN_ON(is_vidmem_page_alloc(iova)); | ||
1278 | |||
1279 | if (nvgpu_iommuable(g) && g->ops.mm.get_physical_addr_bits) | ||
1280 | return iova | 1ULL << g->ops.mm.get_physical_addr_bits(g); | ||
1281 | |||
1282 | return iova; | ||
1283 | } | ||
1284 | |||
1285 | /* for gk20a the "video memory" apertures here are misnomers. */ | 1274 | /* for gk20a the "video memory" apertures here are misnomers. */ |
1286 | static inline u32 big_valid_pde0_bits(struct gk20a *g, | 1275 | static inline u32 big_valid_pde0_bits(struct gk20a *g, |
1287 | struct nvgpu_gmmu_pd *pd, u64 addr) | 1276 | struct nvgpu_gmmu_pd *pd, u64 addr) |
@@ -2170,7 +2159,7 @@ int gk20a_mm_suspend(struct gk20a *g) | |||
2170 | return 0; | 2159 | return 0; |
2171 | } | 2160 | } |
2172 | 2161 | ||
2173 | u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g) | 2162 | u32 gk20a_mm_get_iommu_bit(struct gk20a *g) |
2174 | { | 2163 | { |
2175 | return 34; | 2164 | return 34; |
2176 | } | 2165 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 13a3dcd0..9f03a495 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -342,8 +342,6 @@ void gk20a_mm_dump_vm(struct vm_gk20a *vm, | |||
342 | 342 | ||
343 | int gk20a_mm_suspend(struct gk20a *g); | 343 | int gk20a_mm_suspend(struct gk20a *g); |
344 | 344 | ||
345 | u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova); | ||
346 | |||
347 | void gk20a_mm_ltc_isr(struct gk20a *g); | 345 | void gk20a_mm_ltc_isr(struct gk20a *g); |
348 | 346 | ||
349 | bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g); | 347 | bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g); |
@@ -420,7 +418,7 @@ void pde_range_from_vaddr_range(struct vm_gk20a *vm, | |||
420 | u64 addr_lo, u64 addr_hi, | 418 | u64 addr_lo, u64 addr_hi, |
421 | u32 *pde_lo, u32 *pde_hi); | 419 | u32 *pde_lo, u32 *pde_hi); |
422 | int gk20a_mm_pde_coverage_bit_count(struct vm_gk20a *vm); | 420 | int gk20a_mm_pde_coverage_bit_count(struct vm_gk20a *vm); |
423 | u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g); | 421 | u32 gk20a_mm_get_iommu_bit(struct gk20a *g); |
424 | 422 | ||
425 | const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g, | 423 | const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g, |
426 | u32 big_page_size); | 424 | u32 big_page_size); |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index ceef80bf..98c4ddfb 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -436,7 +436,7 @@ static const struct gpu_ops gm20b_ops = { | |||
436 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | 436 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, |
437 | .get_default_big_page_size = gm20b_mm_get_default_big_page_size, | 437 | .get_default_big_page_size = gm20b_mm_get_default_big_page_size, |
438 | .gpu_phys_addr = gm20b_gpu_phys_addr, | 438 | .gpu_phys_addr = gm20b_gpu_phys_addr, |
439 | .get_physical_addr_bits = gk20a_mm_get_physical_addr_bits, | 439 | .get_iommu_bit = gk20a_mm_get_iommu_bit, |
440 | .get_mmu_levels = gk20a_mm_get_mmu_levels, | 440 | .get_mmu_levels = gk20a_mm_get_mmu_levels, |
441 | .init_pdb = gk20a_mm_init_pdb, | 441 | .init_pdb = gk20a_mm_init_pdb, |
442 | .init_mm_setup_hw = gk20a_init_mm_setup_hw, | 442 | .init_mm_setup_hw = gk20a_init_mm_setup_hw, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 90a513d6..89fe66c9 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -515,7 +515,6 @@ static const struct gpu_ops gp106_ops = { | |||
515 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | 515 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, |
516 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | 516 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, |
517 | .gpu_phys_addr = gm20b_gpu_phys_addr, | 517 | .gpu_phys_addr = gm20b_gpu_phys_addr, |
518 | .get_physical_addr_bits = NULL, | ||
519 | .get_mmu_levels = gp10b_mm_get_mmu_levels, | 518 | .get_mmu_levels = gp10b_mm_get_mmu_levels, |
520 | .init_pdb = gp10b_mm_init_pdb, | 519 | .init_pdb = gp10b_mm_init_pdb, |
521 | .init_mm_setup_hw = gp10b_init_mm_setup_hw, | 520 | .init_mm_setup_hw = gp10b_init_mm_setup_hw, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index e64bb9cc..0db6b3f7 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -478,7 +478,7 @@ static const struct gpu_ops gp10b_ops = { | |||
478 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | 478 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, |
479 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | 479 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, |
480 | .gpu_phys_addr = gm20b_gpu_phys_addr, | 480 | .gpu_phys_addr = gm20b_gpu_phys_addr, |
481 | .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, | 481 | .get_iommu_bit = gp10b_mm_get_iommu_bit, |
482 | .get_mmu_levels = gp10b_mm_get_mmu_levels, | 482 | .get_mmu_levels = gp10b_mm_get_mmu_levels, |
483 | .init_pdb = gp10b_mm_init_pdb, | 483 | .init_pdb = gp10b_mm_init_pdb, |
484 | .init_mm_setup_hw = gp10b_init_mm_setup_hw, | 484 | .init_mm_setup_hw = gp10b_init_mm_setup_hw, |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 96da6cf5..06a9b929 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -41,7 +41,7 @@ u32 gp10b_mm_get_default_big_page_size(void) | |||
41 | return SZ_64K; | 41 | return SZ_64K; |
42 | } | 42 | } |
43 | 43 | ||
44 | u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) | 44 | u32 gp10b_mm_get_iommu_bit(struct gk20a *g) |
45 | { | 45 | { |
46 | return 36; | 46 | return 36; |
47 | } | 47 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index ab59069e..b6bcb04a 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h | |||
@@ -29,7 +29,7 @@ struct nvgpu_mem; | |||
29 | struct vm_gk20a; | 29 | struct vm_gk20a; |
30 | 30 | ||
31 | u32 gp10b_mm_get_default_big_page_size(void); | 31 | u32 gp10b_mm_get_default_big_page_size(void); |
32 | u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g); | 32 | u32 gp10b_mm_get_iommu_bit(struct gk20a *g); |
33 | int gp10b_init_mm_setup_hw(struct gk20a *g); | 33 | int gp10b_init_mm_setup_hw(struct gk20a *g); |
34 | int gb10b_init_bar2_vm(struct gk20a *g); | 34 | int gb10b_init_bar2_vm(struct gk20a *g); |
35 | int gb10b_init_bar2_mm_hw_setup(struct gk20a *g); | 35 | int gb10b_init_bar2_mm_hw_setup(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h index b939cc33..c2f0e37b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h | |||
@@ -298,4 +298,6 @@ u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, | |||
298 | u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, | 298 | u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, |
299 | u32 sysmem_mask, u32 vidmem_mask); | 299 | u32 sysmem_mask, u32 vidmem_mask); |
300 | 300 | ||
301 | u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys); | ||
302 | |||
301 | #endif | 303 | #endif |
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c index 16bfb3a3..49517b9a 100644 --- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c | |||
@@ -379,7 +379,7 @@ void vgpu_init_mm_ops(struct gpu_ops *gops) | |||
379 | gops->mm.l2_invalidate = vgpu_mm_l2_invalidate; | 379 | gops->mm.l2_invalidate = vgpu_mm_l2_invalidate; |
380 | gops->mm.l2_flush = vgpu_mm_l2_flush; | 380 | gops->mm.l2_flush = vgpu_mm_l2_flush; |
381 | gops->fb.tlb_invalidate = vgpu_mm_tlb_invalidate; | 381 | gops->fb.tlb_invalidate = vgpu_mm_tlb_invalidate; |
382 | gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; | 382 | gops->mm.get_iommu_bit = gk20a_mm_get_iommu_bit; |
383 | gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr; | 383 | gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr; |
384 | gops->mm.init_mm_setup_hw = NULL; | 384 | gops->mm.init_mm_setup_hw = NULL; |
385 | } | 385 | } |