diff options
author | Vijayakumar <vsubbu@nvidia.com> | 2016-11-04 06:58:29 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-12-19 18:40:30 -0500 |
commit | ed6e707603466b88c81eb8eeceb172b4748fb795 (patch) | |
tree | df494dc61fb346f5d76777a7ee5f70bc9bce9745 /drivers/gpu/nvgpu | |
parent | cee118c1d449793d925231e8ea3bb34558e9c020 (diff) |
gpu: nvgpu: add clk freq controller support
JIRA DNVGPU-127
Add pmu interface structure and command definitions
Change-Id: I5bb84f47057094f55f3adf2c5755416f430aba89
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1248207
(cherry picked from commit ad385eb3ce8ffb2d55ae312901c9dcc4e1543b14)
Reviewed-on: http://git-master/r/1267433
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifclk.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h index d1e5e53e..70f26707 100644 --- a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h +++ b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h | |||
@@ -46,6 +46,7 @@ enum nv_pmu_clk_clkwhich { | |||
46 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02 | 46 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02 |
47 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03 | 47 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03 |
48 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04 | 48 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04 |
49 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER 0x05 | ||
49 | 50 | ||
50 | /*! | 51 | /*! |
51 | * CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the | 52 | * CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the |
@@ -309,6 +310,48 @@ struct nv_pmu_clk_load { | |||
309 | struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; | 310 | struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; |
310 | } payload; | 311 | } payload; |
311 | }; | 312 | }; |
313 | /* CLK_FREQ_CONTROLLER */ | ||
314 | #define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003) | ||
315 | |||
316 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO (0x00000000) | ||
317 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002) | ||
318 | |||
319 | struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header { | ||
320 | struct nv_pmu_boardobjgrp_e32 super; | ||
321 | u32 sampling_period_ms; | ||
322 | u8 volt_policy_idx; | ||
323 | }; | ||
324 | |||
325 | struct nv_pmu_clk_clk_freq_controller_boardobj_set { | ||
326 | struct nv_pmu_boardobj super; | ||
327 | u8 controller_id; | ||
328 | u8 parts_freq_mode; | ||
329 | bool bdisable; | ||
330 | u32 clk_domain; | ||
331 | s16 freq_cap_noise_unaware_vmin_above; | ||
332 | s16 freq_cap_noise_unaware_vmin_below; | ||
333 | s16 freq_hyst_pos_mhz; | ||
334 | s16 freq_hyst_neg_mhz; | ||
335 | }; | ||
336 | |||
337 | struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set { | ||
338 | struct nv_pmu_clk_clk_freq_controller_boardobj_set super; | ||
339 | s32 prop_gain; | ||
340 | s32 integ_gain; | ||
341 | s32 integ_decay; | ||
342 | s32 volt_delta_min; | ||
343 | s32 volt_delta_max; | ||
344 | u8 slowdown_pct_min; | ||
345 | bool bpoison; | ||
346 | }; | ||
347 | |||
348 | union nv_pmu_clk_clk_freq_controller_boardobj_set_union { | ||
349 | struct nv_pmu_boardobj board_obj; | ||
350 | struct nv_pmu_clk_clk_freq_controller_boardobj_set super; | ||
351 | struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi; | ||
352 | }; | ||
353 | |||
354 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); | ||
312 | 355 | ||
313 | /* CLK CMD ID definitions. */ | 356 | /* CLK CMD ID definitions. */ |
314 | #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) | 357 | #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) |