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authorSunny He <suhe@nvidia.com>2017-06-27 16:42:33 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-13 03:09:08 -0400
commite78153ea1b6b610f2307b86fc42ea33d678b250f (patch)
tree004e16c6b81c4b209cc2714e8722209db92edc2c /drivers/gpu/nvgpu
parentecf67ebbf69a9ab6481b1517b8920f7ac5828bb5 (diff)
gpu: nvgpu: Reorg mc HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I26d74c14661a193af7e8d90dd672b73010e5f841 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509601 GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/Makefile.nvgpu1
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c20
-rw-r--r--drivers/gpu/nvgpu/gm20b/mc_gm20b.c36
-rw-r--r--drivers/gpu/nvgpu/gm20b/mc_gm20b.h18
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c20
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c19
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.c20
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.h11
8 files changed, 66 insertions, 79 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu
index 4aaf7bc5..c754fbd4 100644
--- a/drivers/gpu/nvgpu/Makefile.nvgpu
+++ b/drivers/gpu/nvgpu/Makefile.nvgpu
@@ -110,7 +110,6 @@ nvgpu-y := \
110 gm20b/pmu_gm20b.o \ 110 gm20b/pmu_gm20b.o \
111 gm20b/mm_gm20b.o \ 111 gm20b/mm_gm20b.o \
112 gm20b/regops_gm20b.o \ 112 gm20b/regops_gm20b.o \
113 gm20b/mc_gm20b.o \
114 gm20b/cde_gm20b.o \ 113 gm20b/cde_gm20b.o \
115 gm20b/therm_gm20b.o \ 114 gm20b/therm_gm20b.o \
116 gm206/bios_gm206.o \ 115 gm206/bios_gm206.o \
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index c6c7b590..4baed828 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -16,6 +16,7 @@
16#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
17#include "gk20a/dbg_gpu_gk20a.h" 17#include "gk20a/dbg_gpu_gk20a.h"
18#include "gk20a/css_gr_gk20a.h" 18#include "gk20a/css_gr_gk20a.h"
19#include "gk20a/mc_gk20a.h"
19#include "gk20a/bus_gk20a.h" 20#include "gk20a/bus_gk20a.h"
20#include "gk20a/flcn_gk20a.h" 21#include "gk20a/flcn_gk20a.h"
21#include "gk20a/priv_ring_gk20a.h" 22#include "gk20a/priv_ring_gk20a.h"
@@ -31,7 +32,6 @@
31#include "mm_gm20b.h" 32#include "mm_gm20b.h"
32#include "pmu_gm20b.h" 33#include "pmu_gm20b.h"
33#include "clk_gm20b.h" 34#include "clk_gm20b.h"
34#include "mc_gm20b.h"
35#include "regops_gm20b.h" 35#include "regops_gm20b.h"
36#include "cde_gm20b.h" 36#include "cde_gm20b.h"
37#include "therm_gm20b.h" 37#include "therm_gm20b.h"
@@ -199,6 +199,22 @@ static const struct gpu_ops gm20b_ops = {
199 .pg_gr_load_gating_prod = 199 .pg_gr_load_gating_prod =
200 gr_gm20b_pg_gr_load_gating_prod, 200 gr_gm20b_pg_gr_load_gating_prod,
201 }, 201 },
202 .mc = {
203 .intr_enable = mc_gk20a_intr_enable,
204 .intr_unit_config = mc_gk20a_intr_unit_config,
205 .isr_stall = mc_gk20a_isr_stall,
206 .intr_stall = mc_gk20a_intr_stall,
207 .intr_stall_pause = mc_gk20a_intr_stall_pause,
208 .intr_stall_resume = mc_gk20a_intr_stall_resume,
209 .intr_nonstall = mc_gk20a_intr_nonstall,
210 .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause,
211 .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume,
212 .enable = gk20a_mc_enable,
213 .disable = gk20a_mc_disable,
214 .reset = gk20a_mc_reset,
215 .boot_0 = gk20a_mc_boot_0,
216 .is_intr1_pending = mc_gk20a_is_intr1_pending,
217 },
202 .cde = { 218 .cde = {
203 .get_program_numbers = gm20b_cde_get_program_numbers, 219 .get_program_numbers = gm20b_cde_get_program_numbers,
204 }, 220 },
@@ -217,6 +233,7 @@ int gm20b_init_hal(struct gk20a *g)
217 233
218 gops->ltc = gm20b_ops.ltc; 234 gops->ltc = gm20b_ops.ltc;
219 gops->clock_gating = gm20b_ops.clock_gating; 235 gops->clock_gating = gm20b_ops.clock_gating;
236 gops->mc = gm20b_ops.mc;
220 gops->cde = gm20b_ops.cde; 237 gops->cde = gm20b_ops.cde;
221 gops->falcon = gm20b_ops.falcon; 238 gops->falcon = gm20b_ops.falcon;
222 239
@@ -255,7 +272,6 @@ int gm20b_init_hal(struct gk20a *g)
255 } 272 }
256#endif 273#endif
257 gk20a_init_bus(gops); 274 gk20a_init_bus(gops);
258 gm20b_init_mc(gops);
259 gk20a_init_priv_ring(gops); 275 gk20a_init_priv_ring(gops);
260 gm20b_init_gr(gops); 276 gm20b_init_gr(gops);
261 gm20b_init_fb(gops); 277 gm20b_init_fb(gops);
diff --git a/drivers/gpu/nvgpu/gm20b/mc_gm20b.c b/drivers/gpu/nvgpu/gm20b/mc_gm20b.c
deleted file mode 100644
index 005ec729..00000000
--- a/drivers/gpu/nvgpu/gm20b/mc_gm20b.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * GK20A memory interface
3 *
4 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h"
17#include "gk20a/mc_gk20a.h"
18#include "mc_gm20b.h"
19
20void gm20b_init_mc(struct gpu_ops *gops)
21{
22 gops->mc.intr_enable = mc_gk20a_intr_enable;
23 gops->mc.intr_unit_config = mc_gk20a_intr_unit_config;
24 gops->mc.isr_stall = mc_gk20a_isr_stall;
25 gops->mc.intr_stall = mc_gk20a_intr_stall;
26 gops->mc.intr_stall_pause = mc_gk20a_intr_stall_pause;
27 gops->mc.intr_stall_resume = mc_gk20a_intr_stall_resume;
28 gops->mc.intr_nonstall = mc_gk20a_intr_nonstall;
29 gops->mc.intr_nonstall_pause = mc_gk20a_intr_nonstall_pause;
30 gops->mc.intr_nonstall_resume = mc_gk20a_intr_nonstall_resume;
31 gops->mc.enable = gk20a_mc_enable;
32 gops->mc.disable = gk20a_mc_disable;
33 gops->mc.reset = gk20a_mc_reset;
34 gops->mc.boot_0 = gk20a_mc_boot_0;
35 gops->mc.is_intr1_pending = mc_gk20a_is_intr1_pending;
36}
diff --git a/drivers/gpu/nvgpu/gm20b/mc_gm20b.h b/drivers/gpu/nvgpu/gm20b/mc_gm20b.h
deleted file mode 100644
index b19bf6fe..00000000
--- a/drivers/gpu/nvgpu/gm20b/mc_gm20b.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef MC_GM20B_H
15#define MC_GM20B_H
16
17void gm20b_init_mc(struct gpu_ops *gops);
18#endif
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 29b52e44..8521bf6d 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -18,6 +18,8 @@
18#include "gk20a/css_gr_gk20a.h" 18#include "gk20a/css_gr_gk20a.h"
19#include "gk20a/bus_gk20a.h" 19#include "gk20a/bus_gk20a.h"
20#include "gk20a/pramin_gk20a.h" 20#include "gk20a/pramin_gk20a.h"
21#include "gk20a/flcn_gk20a.h"
22#include "gk20a/mc_gk20a.h"
21 23
22#include "gp10b/ltc_gp10b.h" 24#include "gp10b/ltc_gp10b.h"
23#include "gp10b/gr_gp10b.h" 25#include "gp10b/gr_gp10b.h"
@@ -239,6 +241,22 @@ static const struct gpu_ops gp106_ops = {
239 .pg_gr_load_gating_prod = 241 .pg_gr_load_gating_prod =
240 gr_gp106_pg_gr_load_gating_prod, 242 gr_gp106_pg_gr_load_gating_prod,
241 }, 243 },
244 .mc = {
245 .intr_enable = mc_gp10b_intr_enable,
246 .intr_unit_config = mc_gp10b_intr_unit_config,
247 .isr_stall = mc_gp10b_isr_stall,
248 .intr_stall = mc_gp10b_intr_stall,
249 .intr_stall_pause = mc_gp10b_intr_stall_pause,
250 .intr_stall_resume = mc_gp10b_intr_stall_resume,
251 .intr_nonstall = mc_gp10b_intr_nonstall,
252 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
253 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
254 .enable = gk20a_mc_enable,
255 .disable = gk20a_mc_disable,
256 .reset = gk20a_mc_reset,
257 .boot_0 = gk20a_mc_boot_0,
258 .is_intr1_pending = mc_gp10b_is_intr1_pending,
259 },
242 .cde = { 260 .cde = {
243 .get_program_numbers = gp10b_cde_get_program_numbers, 261 .get_program_numbers = gp10b_cde_get_program_numbers,
244 .need_scatter_buffer = gp10b_need_scatter_buffer, 262 .need_scatter_buffer = gp10b_need_scatter_buffer,
@@ -276,6 +294,7 @@ int gp106_init_hal(struct gk20a *g)
276 294
277 gops->ltc = gp106_ops.ltc; 295 gops->ltc = gp106_ops.ltc;
278 gops->clock_gating = gp106_ops.clock_gating; 296 gops->clock_gating = gp106_ops.clock_gating;
297 gops->mc = gp106_ops.mc;
279 gops->cde = gp106_ops.cde; 298 gops->cde = gp106_ops.cde;
280 gops->xve = gp106_ops.xve; 299 gops->xve = gp106_ops.xve;
281 gops->falcon = gp106_ops.falcon; 300 gops->falcon = gp106_ops.falcon;
@@ -290,7 +309,6 @@ int gp106_init_hal(struct gk20a *g)
290 gops->securegpccs = 1; 309 gops->securegpccs = 1;
291 gops->pmupstate = true; 310 gops->pmupstate = true;
292 gk20a_init_bus(gops); 311 gk20a_init_bus(gops);
293 gp10b_init_mc(gops);
294 gp10b_init_priv_ring(gops); 312 gp10b_init_priv_ring(gops);
295 gp106_init_gr(gops); 313 gp106_init_gr(gops);
296 gp10b_init_fecs_trace_ops(gops); 314 gp10b_init_fecs_trace_ops(gops);
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index d004cf3d..af1195ea 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -19,6 +19,7 @@
19#include "gk20a/bus_gk20a.h" 19#include "gk20a/bus_gk20a.h"
20#include "gk20a/pramin_gk20a.h" 20#include "gk20a/pramin_gk20a.h"
21#include "gk20a/flcn_gk20a.h" 21#include "gk20a/flcn_gk20a.h"
22#include "gk20a/mc_gk20a.h"
22 23
23#include "gp10b/gr_gp10b.h" 24#include "gp10b/gr_gp10b.h"
24#include "gp10b/fecs_trace_gp10b.h" 25#include "gp10b/fecs_trace_gp10b.h"
@@ -207,6 +208,22 @@ static const struct gpu_ops gp10b_ops = {
207 .pg_gr_load_gating_prod = 208 .pg_gr_load_gating_prod =
208 gr_gp10b_pg_gr_load_gating_prod, 209 gr_gp10b_pg_gr_load_gating_prod,
209 }, 210 },
211 .mc = {
212 .intr_enable = mc_gp10b_intr_enable,
213 .intr_unit_config = mc_gp10b_intr_unit_config,
214 .isr_stall = mc_gp10b_isr_stall,
215 .intr_stall = mc_gp10b_intr_stall,
216 .intr_stall_pause = mc_gp10b_intr_stall_pause,
217 .intr_stall_resume = mc_gp10b_intr_stall_resume,
218 .intr_nonstall = mc_gp10b_intr_nonstall,
219 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
220 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
221 .enable = gk20a_mc_enable,
222 .disable = gk20a_mc_disable,
223 .reset = gk20a_mc_reset,
224 .boot_0 = gk20a_mc_boot_0,
225 .is_intr1_pending = mc_gp10b_is_intr1_pending,
226 },
210 .cde = { 227 .cde = {
211 .get_program_numbers = gp10b_cde_get_program_numbers, 228 .get_program_numbers = gp10b_cde_get_program_numbers,
212 .need_scatter_buffer = gp10b_need_scatter_buffer, 229 .need_scatter_buffer = gp10b_need_scatter_buffer,
@@ -227,6 +244,7 @@ int gp10b_init_hal(struct gk20a *g)
227 244
228 gops->ltc = gp10b_ops.ltc; 245 gops->ltc = gp10b_ops.ltc;
229 gops->clock_gating = gp10b_ops.clock_gating; 246 gops->clock_gating = gp10b_ops.clock_gating;
247 gops->mc = gp10b_ops.mc;
230 gops->cde = gp10b_ops.cde; 248 gops->cde = gp10b_ops.cde;
231 gops->falcon = gp10b_ops.falcon; 249 gops->falcon = gp10b_ops.falcon;
232 250
@@ -274,7 +292,6 @@ int gp10b_init_hal(struct gk20a *g)
274#endif 292#endif
275 293
276 gk20a_init_bus(gops); 294 gk20a_init_bus(gops);
277 gp10b_init_mc(gops);
278 gp10b_init_priv_ring(gops); 295 gp10b_init_priv_ring(gops);
279 gp10b_init_gr(gops); 296 gp10b_init_gr(gops);
280 gp10b_init_fecs_trace_ops(gops); 297 gp10b_init_fecs_trace_ops(gops);
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 39ad8f9b..5a1d5dcc 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -156,7 +156,7 @@ void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
156 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); 156 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
157} 157}
158 158
159static bool mc_gp10b_is_intr1_pending(struct gk20a *g, 159bool mc_gp10b_is_intr1_pending(struct gk20a *g,
160 enum nvgpu_unit unit, u32 mc_intr_1) 160 enum nvgpu_unit unit, u32 mc_intr_1)
161{ 161{
162 u32 mask = 0; 162 u32 mask = 0;
@@ -179,21 +179,3 @@ static bool mc_gp10b_is_intr1_pending(struct gk20a *g,
179 179
180 return is_pending; 180 return is_pending;
181} 181}
182
183void gp10b_init_mc(struct gpu_ops *gops)
184{
185 gops->mc.intr_enable = mc_gp10b_intr_enable;
186 gops->mc.intr_unit_config = mc_gp10b_intr_unit_config;
187 gops->mc.isr_stall = mc_gp10b_isr_stall;
188 gops->mc.intr_stall = mc_gp10b_intr_stall;
189 gops->mc.intr_stall_pause = mc_gp10b_intr_stall_pause;
190 gops->mc.intr_stall_resume = mc_gp10b_intr_stall_resume;
191 gops->mc.intr_nonstall = mc_gp10b_intr_nonstall;
192 gops->mc.intr_nonstall_pause = mc_gp10b_intr_nonstall_pause;
193 gops->mc.intr_nonstall_resume = mc_gp10b_intr_nonstall_resume;
194 gops->mc.enable = gk20a_mc_enable;
195 gops->mc.disable = gk20a_mc_disable;
196 gops->mc.reset = gk20a_mc_reset;
197 gops->mc.boot_0 = gk20a_mc_boot_0;
198 gops->mc.is_intr1_pending = mc_gp10b_is_intr1_pending;
199}
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
index ceba0b39..00e9dd1d 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
@@ -20,9 +20,18 @@ enum MC_INTERRUPT_REGLIST {
20 NVGPU_MC_INTR_NONSTALLING, 20 NVGPU_MC_INTR_NONSTALLING,
21}; 21};
22 22
23void gp10b_init_mc(struct gpu_ops *gops);
24void mc_gp10b_intr_enable(struct gk20a *g); 23void mc_gp10b_intr_enable(struct gk20a *g);
25void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, 24void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
26 bool is_stalling, u32 mask); 25 bool is_stalling, u32 mask);
27void mc_gp10b_isr_stall(struct gk20a *g); 26void mc_gp10b_isr_stall(struct gk20a *g);
27bool mc_gp10b_is_intr1_pending(struct gk20a *g,
28 enum nvgpu_unit unit, u32 mc_intr_1);
29
30u32 mc_gp10b_intr_stall(struct gk20a *g);
31void mc_gp10b_intr_stall_pause(struct gk20a *g);
32void mc_gp10b_intr_stall_resume(struct gk20a *g);
33u32 mc_gp10b_intr_nonstall(struct gk20a *g);
34void mc_gp10b_intr_nonstall_pause(struct gk20a *g);
35void mc_gp10b_intr_nonstall_resume(struct gk20a *g);
36
28#endif 37#endif