diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-08 20:20:26 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-13 01:15:19 -0400 |
commit | df022d27ddf2f66bff04170bb454fa26db8d51b1 (patch) | |
tree | 84f69276f8615330068519b2979b081324fc0484 /drivers/gpu/nvgpu | |
parent | 66fb130bfdf12175c117f36737503b1b5f33d42e (diff) |
gpu: nvgpu: gv11b: support SET_SKEDCHECK s/w methods
Support sw method NVC397_SET_SKEDCHECK and NVC3C0_SET_SKEDCHECK
data fields are
data:0 SKEDCHECK_18_DISABLE
data:1 SKEDCHECK_18_ENABLE
Bug 200315442
Change-Id: I0652434ab0b4d6e49dab94be329072861e99c38c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515772
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 40 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 8 |
2 files changed, 38 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 2c3b0820..6f3b5f0f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -299,8 +299,6 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
299 | 299 | ||
300 | static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) | 300 | static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) |
301 | { | 301 | { |
302 | u32 val; | ||
303 | |||
304 | /* enable exceptions */ | 302 | /* enable exceptions */ |
305 | gk20a_writel(g, gr_fe_hww_esr_r(), | 303 | gk20a_writel(g, gr_fe_hww_esr_r(), |
306 | gr_fe_hww_esr_en_enable_f() | | 304 | gr_fe_hww_esr_en_enable_f() | |
@@ -308,14 +306,6 @@ static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) | |||
308 | gk20a_writel(g, gr_memfmt_hww_esr_r(), | 306 | gk20a_writel(g, gr_memfmt_hww_esr_r(), |
309 | gr_memfmt_hww_esr_en_enable_f() | | 307 | gr_memfmt_hww_esr_en_enable_f() | |
310 | gr_memfmt_hww_esr_reset_active_f()); | 308 | gr_memfmt_hww_esr_reset_active_f()); |
311 | /* WAR for 200315442 */ | ||
312 | val = gk20a_readl(g, gr_sked_hww_esr_en_r()); | ||
313 | val = set_field(val, | ||
314 | gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), | ||
315 | gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f() | ||
316 | ); | ||
317 | nvgpu_log_info(g, "sked_hww_esr_en = 0x%x", val); | ||
318 | gk20a_writel(g, gr_sked_hww_esr_en_r(), val); | ||
319 | } | 309 | } |
320 | 310 | ||
321 | static void gr_gv11b_enable_exceptions(struct gk20a *g) | 311 | static void gr_gv11b_enable_exceptions(struct gk20a *g) |
@@ -1108,6 +1098,30 @@ static void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data) | |||
1108 | gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); | 1098 | gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); |
1109 | } | 1099 | } |
1110 | 1100 | ||
1101 | static void gr_gv11b_set_skedcheck(struct gk20a *g, u32 data) | ||
1102 | { | ||
1103 | u32 reg_val; | ||
1104 | |||
1105 | reg_val = gk20a_readl(g, gr_sked_hww_esr_en_r()); | ||
1106 | |||
1107 | if ((data & NVC397_SET_SKEDCHECK_18_MASK) == | ||
1108 | NVC397_SET_SKEDCHECK_18_DISABLE) { | ||
1109 | reg_val = set_field(reg_val, | ||
1110 | gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), | ||
1111 | gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f() | ||
1112 | ); | ||
1113 | } else if ((data & NVC397_SET_SKEDCHECK_18_MASK) == | ||
1114 | NVC397_SET_SKEDCHECK_18_ENABLE) { | ||
1115 | reg_val = set_field(reg_val, | ||
1116 | gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), | ||
1117 | gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f() | ||
1118 | ); | ||
1119 | } | ||
1120 | nvgpu_log_info(g, "sked_hww_esr_en = 0x%x", reg_val); | ||
1121 | gk20a_writel(g, gr_sked_hww_esr_en_r(), reg_val); | ||
1122 | |||
1123 | } | ||
1124 | |||
1111 | static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) | 1125 | static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) |
1112 | { | 1126 | { |
1113 | gk20a_dbg_fn(""); | 1127 | gk20a_dbg_fn(""); |
@@ -1132,6 +1146,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, | |||
1132 | case NVC0C0_SET_SHADER_EXCEPTIONS: | 1146 | case NVC0C0_SET_SHADER_EXCEPTIONS: |
1133 | gv11b_gr_set_shader_exceptions(g, data); | 1147 | gv11b_gr_set_shader_exceptions(g, data); |
1134 | break; | 1148 | break; |
1149 | case NVC3C0_SET_SKEDCHECK: | ||
1150 | gr_gv11b_set_skedcheck(g, data); | ||
1151 | break; | ||
1135 | default: | 1152 | default: |
1136 | goto fail; | 1153 | goto fail; |
1137 | } | 1154 | } |
@@ -1157,6 +1174,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, | |||
1157 | case NVC397_SET_TEX_IN_DBG: | 1174 | case NVC397_SET_TEX_IN_DBG: |
1158 | gr_gv11b_set_tex_in_dbg(g, data); | 1175 | gr_gv11b_set_tex_in_dbg(g, data); |
1159 | break; | 1176 | break; |
1177 | case NVC397_SET_SKEDCHECK: | ||
1178 | gr_gv11b_set_skedcheck(g, data); | ||
1179 | break; | ||
1160 | default: | 1180 | default: |
1161 | goto fail; | 1181 | goto fail; |
1162 | } | 1182 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index ff5782d9..1e060bd0 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -40,11 +40,19 @@ enum { | |||
40 | #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc | 40 | #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc |
41 | #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c | 41 | #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c |
42 | #define NVC397_SET_TEX_IN_DBG 0x10bc | 42 | #define NVC397_SET_TEX_IN_DBG 0x10bc |
43 | #define NVC397_SET_SKEDCHECK 0x10c0 | ||
43 | 44 | ||
44 | #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 | 45 | #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 |
45 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 | 46 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 |
46 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4 | 47 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4 |
47 | 48 | ||
49 | #define NVC397_SET_SKEDCHECK_18_MASK 0x3 | ||
50 | #define NVC397_SET_SKEDCHECK_18_DEFAULT 0x0 | ||
51 | #define NVC397_SET_SKEDCHECK_18_DISABLE 0x1 | ||
52 | #define NVC397_SET_SKEDCHECK_18_ENABLE 0x2 | ||
53 | |||
54 | #define NVC3C0_SET_SKEDCHECK 0x23c | ||
55 | |||
48 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 | 56 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 |
49 | 57 | ||
50 | void gv11b_init_gr(struct gpu_ops *ops); | 58 | void gv11b_init_gr(struct gpu_ops *ops); |