diff options
author | Sunny He <suhe@nvidia.com> | 2017-06-28 17:16:53 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-26 05:44:23 -0400 |
commit | de3ad1a94974b08268a485136f04b8e436ef2579 (patch) | |
tree | 15910cd769e91f6600fef0546b501faf65e1fa50 /drivers/gpu/nvgpu | |
parent | 92f6eb016cc759b24e249ed6c17cff537cc35db7 (diff) |
gpu: nvgpu: Remove securegpccs flag from gpu_ops
Replace securegpccs boolean flag in gpu_ops with entry in
common flag system.
The new common flag is NVGPU_SEC_SECUREGPCCS
Jira NVGPU-74
Change-Id: I46430f95063f617531cf0e5aba472051b41f4a9d
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514060
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 6 |
9 files changed, 25 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 17a06099..8728c9a7 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -993,7 +993,6 @@ struct gpu_ops { | |||
993 | void (*isr)(struct gk20a *g); | 993 | void (*isr)(struct gk20a *g); |
994 | } priv_ring; | 994 | } priv_ring; |
995 | bool privsecurity; | 995 | bool privsecurity; |
996 | bool securegpccs; | ||
997 | }; | 996 | }; |
998 | 997 | ||
999 | struct nvgpu_bios_ucode { | 998 | struct nvgpu_bios_ucode { |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d0c4dec7..cc57b09f 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -2400,7 +2400,8 @@ static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g) | |||
2400 | return ret; | 2400 | return ret; |
2401 | } | 2401 | } |
2402 | 2402 | ||
2403 | if (g->ops.gr_ctx.use_dma_for_fw_bootstrap || g->ops.securegpccs) | 2403 | if (g->ops.gr_ctx.use_dma_for_fw_bootstrap || |
2404 | nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) | ||
2404 | gk20a_writel(g, gr_fecs_current_ctx_r(), | 2405 | gk20a_writel(g, gr_fecs_current_ctx_r(), |
2405 | gr_fecs_current_ctx_valid_false_f()); | 2406 | gr_fecs_current_ctx_valid_false_f()); |
2406 | 2407 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 1bc51a7c..0d69b5da 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <nvgpu/firmware.h> | 28 | #include <nvgpu/firmware.h> |
29 | #include <nvgpu/pmu.h> | 29 | #include <nvgpu/pmu.h> |
30 | #include <nvgpu/falcon.h> | 30 | #include <nvgpu/falcon.h> |
31 | #include <nvgpu/enabled.h> | ||
31 | 32 | ||
32 | #include <nvgpu/linux/dma.h> | 33 | #include <nvgpu/linux/dma.h> |
33 | 34 | ||
@@ -267,7 +268,7 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
267 | struct nvgpu_firmware *gpccs_sig; | 268 | struct nvgpu_firmware *gpccs_sig; |
268 | int err; | 269 | int err; |
269 | 270 | ||
270 | if (g->ops.securegpccs == false) | 271 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) |
271 | return -ENOENT; | 272 | return -ENOENT; |
272 | 273 | ||
273 | gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, 0); | 274 | gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, 0); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index bd9b627f..5d9cc32c 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -758,7 +758,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
758 | g->ops.pmu.lsfloadedfalconid = 0; | 758 | g->ops.pmu.lsfloadedfalconid = 0; |
759 | if (g->ops.pmu.fecsbootstrapdone) { | 759 | if (g->ops.pmu.fecsbootstrapdone) { |
760 | /* this must be recovery so bootstrap fecs and gpccs */ | 760 | /* this must be recovery so bootstrap fecs and gpccs */ |
761 | if (!g->ops.securegpccs) { | 761 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { |
762 | gr_gm20b_load_gpccs_with_bootloader(g); | 762 | gr_gm20b_load_gpccs_with_bootloader(g); |
763 | err = g->ops.pmu.load_lsfalcon_ucode(g, | 763 | err = g->ops.pmu.load_lsfalcon_ucode(g, |
764 | (1 << LSF_FALCON_ID_FECS)); | 764 | (1 << LSF_FALCON_ID_FECS)); |
@@ -777,7 +777,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
777 | } else { | 777 | } else { |
778 | /* cold boot or rg exit */ | 778 | /* cold boot or rg exit */ |
779 | g->ops.pmu.fecsbootstrapdone = true; | 779 | g->ops.pmu.fecsbootstrapdone = true; |
780 | if (!g->ops.securegpccs) { | 780 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { |
781 | gr_gm20b_load_gpccs_with_bootloader(g); | 781 | gr_gm20b_load_gpccs_with_bootloader(g); |
782 | } else { | 782 | } else { |
783 | /* bind WPR VA inst block */ | 783 | /* bind WPR VA inst block */ |
@@ -797,7 +797,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
797 | } | 797 | } |
798 | 798 | ||
799 | /*start gpccs */ | 799 | /*start gpccs */ |
800 | if (g->ops.securegpccs) { | 800 | if (nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { |
801 | gk20a_writel(g, reg_offset + | 801 | gk20a_writel(g, reg_offset + |
802 | gr_fecs_cpuctl_alias_r(), | 802 | gr_fecs_cpuctl_alias_r(), |
803 | gr_gpccs_cpuctl_startcpu_f(1)); | 803 | gr_gpccs_cpuctl_startcpu_f(1)); |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 7415e6c1..01e277ce 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -351,8 +351,9 @@ int gm20b_init_hal(struct gk20a *g) | |||
351 | gm20b_ops.chip_init_gpu_characteristics; | 351 | gm20b_ops.chip_init_gpu_characteristics; |
352 | gops->get_litter_value = gm20b_ops.get_litter_value; | 352 | gops->get_litter_value = gm20b_ops.get_litter_value; |
353 | 353 | ||
354 | gops->securegpccs = false; | 354 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
355 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 355 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
356 | |||
356 | #ifdef CONFIG_TEGRA_ACR | 357 | #ifdef CONFIG_TEGRA_ACR |
357 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 358 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
358 | gops->privsecurity = 1; | 359 | gops->privsecurity = 1; |
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index dce297bd..929036a3 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include <nvgpu/acr/nvgpu_acr.h> | 21 | #include <nvgpu/acr/nvgpu_acr.h> |
22 | #include <nvgpu/firmware.h> | 22 | #include <nvgpu/firmware.h> |
23 | #include <nvgpu/pmu.h> | 23 | #include <nvgpu/pmu.h> |
24 | #include <nvgpu/enabled.h> | ||
24 | 25 | ||
25 | #include "gk20a/gk20a.h" | 26 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/pmu_gk20a.h" | 27 | #include "gk20a/pmu_gk20a.h" |
@@ -286,7 +287,7 @@ int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | |||
286 | struct nvgpu_firmware *gpccs_sig = NULL; | 287 | struct nvgpu_firmware *gpccs_sig = NULL; |
287 | int err; | 288 | int err; |
288 | 289 | ||
289 | if (g->ops.securegpccs == false) | 290 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) |
290 | return -ENOENT; | 291 | return -ENOENT; |
291 | 292 | ||
292 | switch (ver) { | 293 | switch (ver) { |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 2a661734..80117ede 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -417,7 +417,7 @@ int gp106_init_hal(struct gk20a *g) | |||
417 | gops->bios_init = gp106_ops.bios_init; | 417 | gops->bios_init = gp106_ops.bios_init; |
418 | 418 | ||
419 | gops->privsecurity = 1; | 419 | gops->privsecurity = 1; |
420 | gops->securegpccs = 1; | 420 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
421 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 421 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |
422 | 422 | ||
423 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | 423 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 177a7c9f..818949f0 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -369,36 +369,36 @@ int gp10b_init_hal(struct gk20a *g) | |||
369 | #ifdef CONFIG_TEGRA_ACR | 369 | #ifdef CONFIG_TEGRA_ACR |
370 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 370 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
371 | gops->privsecurity = 0; | 371 | gops->privsecurity = 0; |
372 | gops->securegpccs = 0; | 372 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
373 | } else if (g->is_virtual) { | 373 | } else if (g->is_virtual) { |
374 | gops->privsecurity = 1; | 374 | gops->privsecurity = 1; |
375 | gops->securegpccs = 1; | 375 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
376 | } else { | 376 | } else { |
377 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 377 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
378 | if (val) { | 378 | if (val) { |
379 | gops->privsecurity = 1; | 379 | gops->privsecurity = 1; |
380 | gops->securegpccs =1; | 380 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
381 | } else { | 381 | } else { |
382 | gk20a_dbg_info("priv security is disabled in HW"); | 382 | gk20a_dbg_info("priv security is disabled in HW"); |
383 | gops->privsecurity = 0; | 383 | gops->privsecurity = 0; |
384 | gops->securegpccs = 0; | 384 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
385 | } | 385 | } |
386 | } | 386 | } |
387 | #else | 387 | #else |
388 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 388 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
389 | gk20a_dbg_info("running simulator with PRIV security disabled"); | 389 | gk20a_dbg_info("running simulator with PRIV security disabled"); |
390 | gops->privsecurity = 0; | 390 | gops->privsecurity = 0; |
391 | gops->securegpccs = 0; | 391 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
392 | } else { | 392 | } else { |
393 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 393 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
394 | if (val) { | 394 | if (val) { |
395 | gk20a_dbg_info("priv security is not supported but enabled"); | 395 | gk20a_dbg_info("priv security is not supported but enabled"); |
396 | gops->privsecurity = 1; | 396 | gops->privsecurity = 1; |
397 | gops->securegpccs =1; | 397 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
398 | return -EPERM; | 398 | return -EPERM; |
399 | } else { | 399 | } else { |
400 | gops->privsecurity = 0; | 400 | gops->privsecurity = 0; |
401 | gops->securegpccs = 0; | 401 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
402 | } | 402 | } |
403 | } | 403 | } |
404 | #endif | 404 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 6fa7dcfa..7d495f48 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -38,6 +38,12 @@ struct gk20a; | |||
38 | #define NVGPU_MM_UNIFIED_MEMORY 18 | 38 | #define NVGPU_MM_UNIFIED_MEMORY 18 |
39 | 39 | ||
40 | /* | 40 | /* |
41 | * Security flags | ||
42 | */ | ||
43 | |||
44 | #define NVGPU_SEC_SECUREGPCCS 32 | ||
45 | |||
46 | /* | ||
41 | * PMU flags. | 47 | * PMU flags. |
42 | */ | 48 | */ |
43 | /* perfmon enabled or disabled for PMU */ | 49 | /* perfmon enabled or disabled for PMU */ |