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authorDeepak Nibade <dnibade@nvidia.com>2015-08-17 06:49:09 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2015-08-18 16:53:54 -0400
commitdb8bce518bcf2a1b46e5897f55469f348a16c9a2 (patch)
tree0e6f6391244390e6a665c34cb375aa987a26eaba /drivers/gpu/nvgpu
parent2b0e5ed3615d74afca55454decab79a381dfe5e8 (diff)
gpu: nvgpu: wakeup semaphores after clearing CE2 interrupt
In gk20a_ce2_nonstall_isr(), we first invoke semaphore workqueue on all channels and then clear the interrupt This delay in clearing the interrupt can sometimes lead to dropping of new interrupt If that happens, we never invoke gk20a_channel_semaphore_wakeup() for new semaphore interrupts and semaphore waiting never completes. Fix this by moving gk20a_channel_semaphore_wakeup() after we clear the interrupt Bug 200131938 Change-Id: I26d72f04a8b49f4a3ac326bf6037cd04c741a920 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/784771 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/gk20a/ce2_gk20a.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
index ce23c59a..3a0f20a9 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
@@ -41,8 +41,6 @@ static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
41{ 41{
42 gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); 42 gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
43 43
44 /* wake theads waiting in this channel */
45 gk20a_channel_semaphore_wakeup(g);
46 return ce2_intr_status_nonblockpipe_pending_f(); 44 return ce2_intr_status_nonblockpipe_pending_f();
47} 45}
48 46
@@ -81,14 +79,16 @@ void gk20a_ce2_isr(struct gk20a *g)
81void gk20a_ce2_nonstall_isr(struct gk20a *g) 79void gk20a_ce2_nonstall_isr(struct gk20a *g)
82{ 80{
83 u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); 81 u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
84 u32 clear_intr = 0;
85 82
86 gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); 83 gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
87 84
88 if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) 85 if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) {
89 clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); 86 gk20a_writel(g, ce2_intr_status_r(),
87 ce2_nonblockpipe_isr(g, ce2_intr));
90 88
91 gk20a_writel(g, ce2_intr_status_r(), clear_intr); 89 /* wake threads waiting in this channel */
90 gk20a_channel_semaphore_wakeup(g);
91 }
92 92
93 return; 93 return;
94} 94}