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authorVinod G <vinodg@nvidia.com>2019-02-05 21:05:42 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2020-01-08 11:35:30 -0500
commitdacb06f4647b924aa6455e8156b74df5098cf3bf (patch)
tree46b3e1bbde525c902b881613effd1ae50f8ceae0 /drivers/gpu/nvgpu
parent264691e69d825489e0a0bcee56f700e241186bb4 (diff)
gpu: nvgpu: add platform atomic support
Add new variable in nvgpu_as_map_buffer_ex_args for app to specify the platform atomic support for the page. When platform atomic attribute flag is set, pte memory aperture is set to be coherent type. renamed nvgpu_aperture_mask_coh -> nvgpu_aperture_mask_raw function. bug 200580236 Change-Id: I18266724dafdc8dfd96a0711f23cf08e23682afc Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2012679 (cherry picked from commit 9e0a9004b71f92b7713fd3b30141b0d9d4cfa2c6) Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2274914 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Sreeniketh H <sh@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/common/mm/gmmu.c10
-rw-r--r--drivers/gpu/nvgpu/common/mm/nvgpu_mem.c6
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.c4
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.c34
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c3
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/enabled.h7
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/gmmu.h5
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h4
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/vm.h3
-rw-r--r--drivers/gpu/nvgpu/os/linux/vm.c4
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c3
11 files changed, 61 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c
index afbad75c..a5790e3a 100644
--- a/drivers/gpu/nvgpu/common/mm/gmmu.c
+++ b/drivers/gpu/nvgpu/common/mm/gmmu.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -628,7 +628,7 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm,
628 "vm=%s " 628 "vm=%s "
629 "%-5s GPU virt %#-12llx +%#-9llx phys %#-12llx " 629 "%-5s GPU virt %#-12llx +%#-9llx phys %#-12llx "
630 "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | " 630 "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | "
631 "kind=%#02x APT=%-6s %c%c%c%c%c", 631 "kind=%#02x APT=%-6s %c%c%c%c%c%c",
632 vm->name, 632 vm->name,
633 (sgt != NULL) ? "MAP" : "UNMAP", 633 (sgt != NULL) ? "MAP" : "UNMAP",
634 virt_addr, 634 virt_addr,
@@ -643,7 +643,8 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm,
643 attrs->sparse ? 'S' : '-', 643 attrs->sparse ? 'S' : '-',
644 attrs->priv ? 'P' : '-', 644 attrs->priv ? 'P' : '-',
645 attrs->coherent ? 'I' : '-', 645 attrs->coherent ? 'I' : '-',
646 attrs->valid ? 'V' : '-'); 646 attrs->valid ? 'V' : '-',
647 attrs->platform_atomic ? 'A' : '-');
647 648
648 err = __nvgpu_gmmu_do_update_page_table(vm, 649 err = __nvgpu_gmmu_do_update_page_table(vm,
649 sgt, 650 sgt,
@@ -702,7 +703,8 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
702 .priv = priv, 703 .priv = priv,
703 .coherent = flags & NVGPU_VM_MAP_IO_COHERENT, 704 .coherent = flags & NVGPU_VM_MAP_IO_COHERENT,
704 .valid = (flags & NVGPU_VM_MAP_UNMAPPED_PTE) == 0U, 705 .valid = (flags & NVGPU_VM_MAP_UNMAPPED_PTE) == 0U,
705 .aperture = aperture 706 .aperture = aperture,
707 .platform_atomic = (flags & NVGPU_VM_MAP_PLATFORM_ATOMIC) != 0U
706 }; 708 };
707 709
708 /* 710 /*
diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
index 8f6bd66e..2326e0ae 100644
--- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
+++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -31,7 +31,7 @@
31 * will not add any checks. If you want to simply use the default coherency then 31 * will not add any checks. If you want to simply use the default coherency then
32 * use nvgpu_aperture_mask(). 32 * use nvgpu_aperture_mask().
33 */ 33 */
34u32 nvgpu_aperture_mask_coh(struct gk20a *g, enum nvgpu_aperture aperture, 34u32 nvgpu_aperture_mask_raw(struct gk20a *g, enum nvgpu_aperture aperture,
35 u32 sysmem_mask, u32 sysmem_coh_mask, 35 u32 sysmem_mask, u32 sysmem_coh_mask,
36 u32 vidmem_mask) 36 u32 vidmem_mask)
37{ 37{
@@ -71,7 +71,7 @@ u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem,
71 ap = APERTURE_SYSMEM_COH; 71 ap = APERTURE_SYSMEM_COH;
72 } 72 }
73 73
74 return nvgpu_aperture_mask_coh(g, ap, 74 return nvgpu_aperture_mask_raw(g, ap,
75 sysmem_mask, 75 sysmem_mask,
76 sysmem_coh_mask, 76 sysmem_coh_mask,
77 vidmem_mask); 77 vidmem_mask);
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 644531f1..18922d46 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -222,7 +222,7 @@ static void __update_pte(struct vm_gk20a *vm,
222 pte_w[0] |= gmmu_pte_privilege_true_f(); 222 pte_w[0] |= gmmu_pte_privilege_true_f();
223 } 223 }
224 224
225 pte_w[1] = nvgpu_aperture_mask_coh(g, attrs->aperture, 225 pte_w[1] = nvgpu_aperture_mask_raw(g, attrs->aperture,
226 gmmu_pte_aperture_sys_mem_ncoh_f(), 226 gmmu_pte_aperture_sys_mem_ncoh_f(),
227 gmmu_pte_aperture_sys_mem_coh_f(), 227 gmmu_pte_aperture_sys_mem_coh_f(),
228 gmmu_pte_aperture_video_memory_f()) | 228 gmmu_pte_aperture_video_memory_f()) |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index 2c0056e1..a4b291d8 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP10B MMU 2 * GP10B MMU
3 * 3 *
4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -78,6 +78,32 @@ clean_up_va:
78 return err; 78 return err;
79} 79}
80 80
81/*
82 * For GV11B and TU104 MSS NVLINK HW settings are in force_snoop mode.
83 * This will force all the GPU mappings to be coherent.
84 * By default the mem aperture sets as sysmem_non_coherent and will use L2 mode.
85 * Change target pte aperture to sysmem_coherent if mem attribute requests for
86 * platform atomics to use rmw atomic capability.
87 *
88 */
89static u32 gmmu_aperture_mask(struct gk20a *g,
90 enum nvgpu_aperture mem_ap,
91 bool platform_atomic_attr,
92 u32 sysmem_mask,
93 u32 sysmem_coh_mask,
94 u32 vidmem_mask)
95{
96 if (nvgpu_is_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC) &&
97 platform_atomic_attr) {
98 mem_ap = APERTURE_SYSMEM_COH;
99 }
100
101 return nvgpu_aperture_mask_raw(g, mem_ap,
102 sysmem_mask,
103 sysmem_coh_mask,
104 vidmem_mask);
105}
106
81static void update_gmmu_pde3_locked(struct vm_gk20a *vm, 107static void update_gmmu_pde3_locked(struct vm_gk20a *vm,
82 const struct gk20a_mmu_level *l, 108 const struct gk20a_mmu_level *l,
83 struct nvgpu_gmmu_pd *pd, 109 struct nvgpu_gmmu_pd *pd,
@@ -191,8 +217,9 @@ static void __update_pte(struct vm_gk20a *vm,
191 u32 pte_addr = attrs->aperture == APERTURE_SYSMEM ? 217 u32 pte_addr = attrs->aperture == APERTURE_SYSMEM ?
192 gmmu_new_pte_address_sys_f(phys_shifted) : 218 gmmu_new_pte_address_sys_f(phys_shifted) :
193 gmmu_new_pte_address_vid_f(phys_shifted); 219 gmmu_new_pte_address_vid_f(phys_shifted);
194 u32 pte_tgt = nvgpu_aperture_mask_coh(g, 220 u32 pte_tgt = gmmu_aperture_mask(g,
195 attrs->aperture, 221 attrs->aperture,
222 attrs->platform_atomic,
196 gmmu_new_pte_aperture_sys_mem_ncoh_f(), 223 gmmu_new_pte_aperture_sys_mem_ncoh_f(),
197 gmmu_new_pte_aperture_sys_mem_coh_f(), 224 gmmu_new_pte_aperture_sys_mem_coh_f(),
198 gmmu_new_pte_aperture_video_memory_f()); 225 gmmu_new_pte_aperture_video_memory_f());
@@ -253,7 +280,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
253 "vm=%s " 280 "vm=%s "
254 "PTE: i=%-4u size=%-2u | " 281 "PTE: i=%-4u size=%-2u | "
255 "GPU %#-12llx phys %#-12llx " 282 "GPU %#-12llx phys %#-12llx "
256 "pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c%c " 283 "pgsz: %3dkb perm=%-2s kind=%#02x APT=%-6s %c%c%c%c%c%c "
257 "ctag=0x%08x " 284 "ctag=0x%08x "
258 "[0x%08x, 0x%08x]", 285 "[0x%08x, 0x%08x]",
259 vm->name, 286 vm->name,
@@ -268,6 +295,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
268 attrs->priv ? 'P' : '-', 295 attrs->priv ? 'P' : '-',
269 attrs->coherent ? 'I' : '-', 296 attrs->coherent ? 'I' : '-',
270 attrs->valid ? 'V' : '-', 297 attrs->valid ? 'V' : '-',
298 attrs->platform_atomic ? 'A' : '-',
271 (u32)attrs->ctag / g->ops.fb.compression_page_size(g), 299 (u32)attrs->ctag / g->ops.fb.compression_page_size(g),
272 pte_w[1], pte_w[0]); 300 pte_w[1], pte_w[0]);
273 301
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 4f298133..68ea78a6 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B Tegra HAL interface 2 * GV11B Tegra HAL interface
3 * 3 *
4 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -957,6 +957,7 @@ int gv11b_init_hal(struct gk20a *g)
957 __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true); 957 __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true);
958 958
959 __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); 959 __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
960 __nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true);
960 961
961 g->name = "gv11b"; 962 g->name = "gv11b";
962 963
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index 76f0f2bd..fc7bab90 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -178,10 +178,13 @@ struct gk20a;
178/* NVGPU_GPU_IOCTL_GET_GPU_LOAD is available */ 178/* NVGPU_GPU_IOCTL_GET_GPU_LOAD is available */
179#define NVGPU_SUPPORT_GET_GPU_LOAD 70 179#define NVGPU_SUPPORT_GET_GPU_LOAD 70
180 180
181/* PLATFORM_ATOMIC support */
182#define NVGPU_SUPPORT_PLATFORM_ATOMIC 71
183
181/* 184/*
182 * Must be greater than the largest bit offset in the above list. 185 * Must be greater than the largest bit offset in the above list.
183 */ 186 */
184#define NVGPU_MAX_ENABLED_BITS 71 187#define NVGPU_MAX_ENABLED_BITS 72
185 188
186/** 189/**
187 * nvgpu_is_enabled - Check if the passed flag is enabled. 190 * nvgpu_is_enabled - Check if the passed flag is enabled.
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
index a70015f8..66cb5218 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -155,6 +155,7 @@ struct nvgpu_gmmu_pd {
155 * valid: Set if the PTE should be marked valid. 155 * valid: Set if the PTE should be marked valid.
156 * aperture: VIDMEM or SYSMEM. 156 * aperture: VIDMEM or SYSMEM.
157 * debug: When set print debugging info. 157 * debug: When set print debugging info.
158 * platform_atomic: True if platform_atomic flag is valid.
158 * 159 *
159 * These fields are dynamically updated as necessary during the map: 160 * These fields are dynamically updated as necessary during the map:
160 * 161 *
@@ -173,8 +174,8 @@ struct nvgpu_gmmu_attrs {
173 bool valid; 174 bool valid;
174 enum nvgpu_aperture aperture; 175 enum nvgpu_aperture aperture;
175 bool debug; 176 bool debug;
176
177 bool l3_alloc; 177 bool l3_alloc;
178 bool platform_atomic;
178}; 179};
179 180
180struct gk20a_mmu_level { 181struct gk20a_mmu_level {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
index 8e62a1d6..4e84f2af 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -349,7 +349,7 @@ void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
349u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem); 349u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem);
350u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem); 350u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem);
351 351
352u32 nvgpu_aperture_mask_coh(struct gk20a *g, enum nvgpu_aperture aperture, 352u32 nvgpu_aperture_mask_raw(struct gk20a *g, enum nvgpu_aperture aperture,
353 u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); 353 u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask);
354u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, 354u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem,
355 u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); 355 u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h
index 66749717..3867c745 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -213,6 +213,7 @@ struct vm_gk20a {
213#define NVGPU_VM_MAP_UNMAPPED_PTE BIT32(3) 213#define NVGPU_VM_MAP_UNMAPPED_PTE BIT32(3)
214#define NVGPU_VM_MAP_DIRECT_KIND_CTRL BIT32(4) 214#define NVGPU_VM_MAP_DIRECT_KIND_CTRL BIT32(4)
215#define NVGPU_VM_MAP_L3_ALLOC BIT32(5) 215#define NVGPU_VM_MAP_L3_ALLOC BIT32(5)
216#define NVGPU_VM_MAP_PLATFORM_ATOMIC BIT32(6)
216 217
217#define NVGPU_KIND_INVALID -1 218#define NVGPU_KIND_INVALID -1
218 219
diff --git a/drivers/gpu/nvgpu/os/linux/vm.c b/drivers/gpu/nvgpu/os/linux/vm.c
index 27a91cf6..dc807ab6 100644
--- a/drivers/gpu/nvgpu/os/linux/vm.c
+++ b/drivers/gpu/nvgpu/os/linux/vm.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -54,6 +54,8 @@ static u32 nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags)
54 core_flags |= NVGPU_VM_MAP_L3_ALLOC; 54 core_flags |= NVGPU_VM_MAP_L3_ALLOC;
55 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL) 55 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL)
56 core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL; 56 core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL;
57 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC)
58 core_flags |= NVGPU_VM_MAP_PLATFORM_ATOMIC;
57 59
58 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS) 60 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS)
59 nvgpu_warn(g, "Ignoring deprecated flag: " 61 nvgpu_warn(g, "Ignoring deprecated flag: "
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c
index 1bcd151a..baddae13 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -43,6 +43,7 @@ int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g)
43 __nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true); 43 __nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
44 __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true); 44 __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
45 __nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true); 45 __nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
46 __nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true);
46 47
47 return 0; 48 return 0;
48} 49}