diff options
author | Shreshtha SAHU <ssahu@nvidia.com> | 2016-11-10 04:02:10 -0500 |
---|---|---|
committer | Shreshtha Sahu <ssahu@nvidia.com> | 2016-11-14 22:19:52 -0500 |
commit | daaa9f030cb00ca692f644bc485958fb21c43a62 (patch) | |
tree | f2afc84fd507634a4c3802c695f30637e550bfb6 /drivers/gpu/nvgpu | |
parent | 1ba169d7dbea1f0e9254cbd285e92ff51235b7c0 (diff) |
gpu: nvgpu: gm20b: add fuse clock for GPU
Bug: 200233943
Change-Id: I8eb2f3cf45b23d7d4e30bf4d5dfc2d6f09c8481e
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/1250979
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/platform_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c | 13 |
2 files changed, 16 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h index c0b847e5..94b8d157 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h | |||
@@ -19,6 +19,8 @@ | |||
19 | #include <linux/device.h> | 19 | #include <linux/device.h> |
20 | #include <linux/dma-attrs.h> | 20 | #include <linux/dma-attrs.h> |
21 | 21 | ||
22 | #define GK20A_CLKS_MAX 4 | ||
23 | |||
22 | struct gk20a; | 24 | struct gk20a; |
23 | struct channel_gk20a; | 25 | struct channel_gk20a; |
24 | struct gr_ctx_buffer_desc; | 26 | struct gr_ctx_buffer_desc; |
@@ -65,7 +67,7 @@ struct gk20a_platform { | |||
65 | 67 | ||
66 | /* Clock configuration is stored here. Platform probe is responsible | 68 | /* Clock configuration is stored here. Platform probe is responsible |
67 | * for filling this data. */ | 69 | * for filling this data. */ |
68 | struct clk *clk[3]; | 70 | struct clk *clk[GK20A_CLKS_MAX]; |
69 | int num_clks; | 71 | int num_clks; |
70 | 72 | ||
71 | #ifdef CONFIG_RESET_CONTROLLER | 73 | #ifdef CONFIG_RESET_CONTROLLER |
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c index 933fe2d8..40e7cead 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c | |||
@@ -492,6 +492,8 @@ static int gm20b_tegra_railgate(struct device *dev) | |||
492 | clk_disable_unprepare(platform->clk_reset); | 492 | clk_disable_unprepare(platform->clk_reset); |
493 | clk_disable_unprepare(platform->clk[0]); | 493 | clk_disable_unprepare(platform->clk[0]); |
494 | clk_disable_unprepare(platform->clk[1]); | 494 | clk_disable_unprepare(platform->clk[1]); |
495 | if (platform->clk[3]) | ||
496 | clk_disable_unprepare(platform->clk[3]); | ||
495 | 497 | ||
496 | udelay(10); | 498 | udelay(10); |
497 | 499 | ||
@@ -569,6 +571,14 @@ static int gm20b_tegra_unrailgate(struct device *dev) | |||
569 | gk20a_err(dev, "could not turn on pwr clock"); | 571 | gk20a_err(dev, "could not turn on pwr clock"); |
570 | goto err_clk_on; | 572 | goto err_clk_on; |
571 | } | 573 | } |
574 | |||
575 | if (platform->clk[3]) { | ||
576 | ret = clk_prepare_enable(platform->clk[3]); | ||
577 | if (ret) { | ||
578 | gk20a_err(dev, "could not turn on fuse clock"); | ||
579 | goto err_clk_on; | ||
580 | } | ||
581 | } | ||
572 | } | 582 | } |
573 | 583 | ||
574 | udelay(10); | 584 | udelay(10); |
@@ -617,6 +627,7 @@ static struct { | |||
617 | {"gpu_ref", UINT_MAX}, | 627 | {"gpu_ref", UINT_MAX}, |
618 | {"pll_p_out5", 204000000}, | 628 | {"pll_p_out5", 204000000}, |
619 | {"emc", UINT_MAX}, | 629 | {"emc", UINT_MAX}, |
630 | {"fuse", UINT_MAX}, | ||
620 | #endif | 631 | #endif |
621 | }; | 632 | }; |
622 | 633 | ||
@@ -636,6 +647,8 @@ static int gk20a_tegra_get_clocks(struct device *dev) | |||
636 | int i; | 647 | int i; |
637 | int ret = 0; | 648 | int ret = 0; |
638 | 649 | ||
650 | BUG_ON(GK20A_CLKS_MAX < ARRAY_SIZE(tegra_gk20a_clocks)); | ||
651 | |||
639 | snprintf(devname, sizeof(devname), "tegra_%s", dev_name(dev)); | 652 | snprintf(devname, sizeof(devname), "tegra_%s", dev_name(dev)); |
640 | 653 | ||
641 | platform->num_clks = 0; | 654 | platform->num_clks = 0; |