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authorDebarshi Dutta <ddutta@nvidia.com>2018-11-29 04:41:15 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2019-02-11 11:18:40 -0500
commitd9efcd587162b50582eb2b2bbaad2b8bc0180446 (patch)
tree00eda6e411bcecb1795e5264e6ef5500adc336ec /drivers/gpu/nvgpu
parentef9de9e9925573b691d78760e42334ad24c5797f (diff)
gpu: nvgpu: replace input parameter tsgid with pointer to struct tsg_gk20a
The function gk20a_fifo_recover_tsg has to pass a valid struct tsg to other functions from within. This qualifies it to have a pointer to struct tsg_gk20a as an input parameter. Tsg specific parts of the gk20a_fifo_preempt_timeout_rc are now moved into another function gk20a_fifo_preempt_timeout_rc_tsg that takes a tsg as an input and passes it to gk20a_fifo_recover_tsg. The pointer to a tsg is also used to enumerate channels from within. The function gk20a_fifo_preempt_timeout_rc now contains only channel specific code. Jira NVGPU-1461 Change-Id: Ice0a9921567841fb5586a7e4e010c442ca6cf172 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1961675 (cherry picked from commit e19cea7ab3ef688186222dec940c2396536408ce in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2013726 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c83
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.h8
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c2
3 files changed, 42 insertions, 51 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index a2ebb720..710313bf 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1975,8 +1975,8 @@ void gk20a_fifo_recover_ch(struct gk20a *g, u32 chid, bool verbose, int rc_type)
1975 nvgpu_mutex_release(&g->dbg_sessions_lock); 1975 nvgpu_mutex_release(&g->dbg_sessions_lock);
1976} 1976}
1977 1977
1978void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose, 1978void gk20a_fifo_recover_tsg(struct gk20a *g, struct tsg_gk20a *tsg,
1979 int rc_type) 1979 bool verbose, u32 rc_type)
1980{ 1980{
1981 u32 engines; 1981 u32 engines;
1982 1982
@@ -1985,14 +1985,12 @@ void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose,
1985 nvgpu_mutex_acquire(&g->dbg_sessions_lock); 1985 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
1986 gr_gk20a_disable_ctxsw(g); 1986 gr_gk20a_disable_ctxsw(g);
1987 1987
1988 engines = gk20a_fifo_engines_on_id(g, tsgid, true); 1988 engines = gk20a_fifo_engines_on_id(g, tsg->tsgid, true);
1989 1989
1990 if (engines) { 1990 if (engines) {
1991 gk20a_fifo_recover(g, engines, tsgid, true, true, verbose, 1991 gk20a_fifo_recover(g, engines, tsg->tsgid, true, true, verbose,
1992 rc_type); 1992 rc_type);
1993 } else { 1993 } else {
1994 struct tsg_gk20a *tsg = &g->fifo.tsg[tsgid];
1995
1996 if (gk20a_fifo_error_tsg(g, tsg) && verbose) { 1994 if (gk20a_fifo_error_tsg(g, tsg) && verbose) {
1997 gk20a_debug_dump(g); 1995 gk20a_debug_dump(g);
1998 } 1996 }
@@ -2127,12 +2125,12 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids,
2127int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, 2125int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch,
2128 u32 err_code, bool verbose) 2126 u32 err_code, bool verbose)
2129{ 2127{
2130 struct tsg_gk20a *tsg = NULL;
2131 struct channel_gk20a *ch_tsg = NULL; 2128 struct channel_gk20a *ch_tsg = NULL;
2132 struct gk20a *g = ch->g; 2129 struct gk20a *g = ch->g;
2133 2130
2134 if (gk20a_is_channel_marked_as_tsg(ch)) { 2131 struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch);
2135 tsg = &g->fifo.tsg[ch->tsgid]; 2132
2133 if (tsg != NULL) {
2136 2134
2137 nvgpu_rwsem_down_read(&tsg->ch_list_lock); 2135 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
2138 2136
@@ -2146,7 +2144,7 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch,
2146 } 2144 }
2147 2145
2148 nvgpu_rwsem_up_read(&tsg->ch_list_lock); 2146 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
2149 gk20a_fifo_recover_tsg(g, ch->tsgid, verbose, 2147 gk20a_fifo_recover_tsg(g, tsg, verbose,
2150 RC_TYPE_FORCE_RESET); 2148 RC_TYPE_FORCE_RESET);
2151 } else { 2149 } else {
2152 g->ops.fifo.set_error_notifier(ch, err_code); 2150 g->ops.fifo.set_error_notifier(ch, err_code);
@@ -2731,7 +2729,7 @@ static void gk20a_fifo_pbdma_fault_rc(struct gk20a *g,
2731 } 2729 }
2732 } 2730 }
2733 nvgpu_rwsem_up_read(&tsg->ch_list_lock); 2731 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
2734 gk20a_fifo_recover_tsg(g, id, true, RC_TYPE_PBDMA_FAULT); 2732 gk20a_fifo_recover_tsg(g, tsg, true, RC_TYPE_PBDMA_FAULT);
2735 } 2733 }
2736} 2734}
2737 2735
@@ -2899,42 +2897,38 @@ int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
2899 return ret; 2897 return ret;
2900} 2898}
2901 2899
2902void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, u32 id, 2900void gk20a_fifo_preempt_timeout_rc_tsg(struct gk20a *g, struct tsg_gk20a *tsg)
2903 unsigned int id_type)
2904{ 2901{
2905 if (id_type == ID_TYPE_TSG) { 2902 struct channel_gk20a *ch = NULL;
2906 struct tsg_gk20a *tsg = &g->fifo.tsg[id];
2907 struct channel_gk20a *ch = NULL;
2908 2903
2909 nvgpu_err(g, 2904 nvgpu_err(g, "preempt TSG %d timeout", tsg->tsgid);
2910 "preempt TSG %d timeout", id);
2911 2905
2912 nvgpu_rwsem_down_read(&tsg->ch_list_lock); 2906 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
2913 nvgpu_list_for_each_entry(ch, &tsg->ch_list, 2907 nvgpu_list_for_each_entry(ch, &tsg->ch_list,
2914 channel_gk20a, ch_entry) { 2908 channel_gk20a, ch_entry) {
2915 if (!gk20a_channel_get(ch)) { 2909 if (!gk20a_channel_get(ch)) {
2916 continue; 2910 continue;
2917 }
2918 g->ops.fifo.set_error_notifier(ch,
2919 NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT);
2920 gk20a_channel_put(ch);
2921 } 2911 }
2922 nvgpu_rwsem_up_read(&tsg->ch_list_lock); 2912 g->ops.fifo.set_error_notifier(ch,
2923 gk20a_fifo_recover_tsg(g, id, true, 2913 NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT);
2924 RC_TYPE_PREEMPT_TIMEOUT); 2914 gk20a_channel_put(ch);
2925 } else { 2915 }
2926 struct channel_gk20a *ch = gk20a_channel_from_id(g, id); 2916 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
2917 gk20a_fifo_recover_tsg(g, tsg, true, RC_TYPE_PREEMPT_TIMEOUT);
2918}
2927 2919
2928 nvgpu_err(g, 2920void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, u32 chid)
2929 "preempt channel %d timeout", id); 2921{
2922 struct channel_gk20a *ch = gk20a_channel_from_id(g, chid);
2930 2923
2931 if (ch != NULL) { 2924 nvgpu_err(g, "preempt channel %d timeout", chid);
2932 g->ops.fifo.set_error_notifier(ch, 2925
2933 NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); 2926 if (ch != NULL) {
2934 gk20a_fifo_recover_ch(g, id, true, 2927 g->ops.fifo.set_error_notifier(ch,
2935 RC_TYPE_PREEMPT_TIMEOUT); 2928 NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT);
2936 gk20a_channel_put(ch); 2929 gk20a_fifo_recover_ch(g, chid, true,
2937 } 2930 RC_TYPE_PREEMPT_TIMEOUT);
2931 gk20a_channel_put(ch);
2938 } 2932 }
2939} 2933}
2940 2934
@@ -2991,12 +2985,10 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid)
2991 nvgpu_err(g, "preempt timed out for chid: %u, " 2985 nvgpu_err(g, "preempt timed out for chid: %u, "
2992 "ctxsw timeout will trigger recovery if needed", chid); 2986 "ctxsw timeout will trigger recovery if needed", chid);
2993 } else { 2987 } else {
2994 gk20a_fifo_preempt_timeout_rc(g, chid, false); 2988 gk20a_fifo_preempt_timeout_rc(g, chid);
2995 } 2989 }
2996 } 2990 }
2997 2991
2998
2999
3000 return ret; 2992 return ret;
3001} 2993}
3002 2994
@@ -3033,8 +3025,7 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg)
3033 "ctxsw timeout will trigger recovery if needed", 3025 "ctxsw timeout will trigger recovery if needed",
3034 tsg->tsgid); 3026 tsg->tsgid);
3035 } else { 3027 } else {
3036 gk20a_fifo_preempt_timeout_rc(g, 3028 gk20a_fifo_preempt_timeout_rc_tsg(g, tsg);
3037 tsg->tsgid, ID_TYPE_TSG);
3038 } 3029 }
3039 } 3030 }
3040 3031
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 2d1c9cc3..12970558 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -268,8 +268,8 @@ void gk20a_fifo_recover(struct gk20a *g,
268 bool id_is_known, bool verbose, int rc_type); 268 bool id_is_known, bool verbose, int rc_type);
269void gk20a_fifo_recover_ch(struct gk20a *g, u32 chid, bool verbose, 269void gk20a_fifo_recover_ch(struct gk20a *g, u32 chid, bool verbose,
270 int rc_type); 270 int rc_type);
271void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose, 271void gk20a_fifo_recover_tsg(struct gk20a *g, struct tsg_gk20a *tsg,
272 int rc_type); 272 bool verbose, u32 rc_type);
273int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, 273int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch,
274 u32 err_code, bool verbose); 274 u32 err_code, bool verbose);
275void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id); 275void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id);
@@ -390,8 +390,8 @@ u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g);
390int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, 390int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
391 unsigned int id_type); 391 unsigned int id_type);
392int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg); 392int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg);
393void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, u32 id, 393void gk20a_fifo_preempt_timeout_rc_tsg(struct gk20a *g, struct tsg_gk20a *tsg);
394 unsigned int id_type); 394void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, u32 chid);
395int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, 395int gk20a_fifo_setup_ramfc(struct channel_gk20a *c,
396 u64 gpfifo_base, u32 gpfifo_entries, 396 u64 gpfifo_base, u32 gpfifo_entries,
397 unsigned long timeout, u32 flags); 397 unsigned long timeout, u32 flags);
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index 11ccdd48..fb9c7712 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -882,7 +882,7 @@ int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg)
882 nvgpu_err(g, "preempt timed out for tsgid: %u, " 882 nvgpu_err(g, "preempt timed out for tsgid: %u, "
883 "ctxsw timeout will trigger recovery if needed", tsg->tsgid); 883 "ctxsw timeout will trigger recovery if needed", tsg->tsgid);
884 } else { 884 } else {
885 gk20a_fifo_preempt_timeout_rc(g, tsg->tsgid, true); 885 gk20a_fifo_preempt_timeout_rc_tsg(g, tsg);
886 } 886 }
887 } 887 }
888 888