diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-09-19 02:34:01 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:23 -0400 |
commit | d65f23cb9ad9d270560ec00c775e60ab559e8e93 (patch) | |
tree | 8a10da4e6a60665a38fef302565b80c5b6af93de /drivers/gpu/nvgpu | |
parent | b05d85a29da43c62a0ca1113ba6a9ab14ceb1a1c (diff) |
gpu: nvgpu: Support 512 channels in gm20b
Retrieve channel count from gm20b specific header instead of the
gk20a header. This increases channel count from 128 to 512.
Change-Id: I96d4887432852795f7f526e33f0d3d2458f3af0e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500623
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 6 |
3 files changed, 14 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 3224e29c..0c8bc6f4 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -513,7 +513,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g) | |||
513 | mutex_init(&f->intr.isr.mutex); | 513 | mutex_init(&f->intr.isr.mutex); |
514 | gk20a_init_fifo_pbdma_intr_descs(f); /* just filling in data/tables */ | 514 | gk20a_init_fifo_pbdma_intr_descs(f); /* just filling in data/tables */ |
515 | 515 | ||
516 | f->num_channels = ccsr_channel__size_1_v(); | 516 | f->num_channels = g->ops.fifo.get_num_fifos(g); |
517 | f->num_pbdma = proj_host_num_pbdma_v(); | 517 | f->num_pbdma = proj_host_num_pbdma_v(); |
518 | f->max_engines = ENGINE_INVAL_GK20A; | 518 | f->max_engines = ENGINE_INVAL_GK20A; |
519 | 519 | ||
@@ -2132,6 +2132,11 @@ static void gk20a_fifo_apply_pb_timeout(struct gk20a *g) | |||
2132 | } | 2132 | } |
2133 | } | 2133 | } |
2134 | 2134 | ||
2135 | static u32 gk20a_fifo_get_num_fifos(struct gk20a *g) | ||
2136 | { | ||
2137 | return ccsr_channel__size_1_v(); | ||
2138 | } | ||
2139 | |||
2135 | void gk20a_init_fifo(struct gpu_ops *gops) | 2140 | void gk20a_init_fifo(struct gpu_ops *gops) |
2136 | { | 2141 | { |
2137 | gk20a_init_channel(gops); | 2142 | gk20a_init_channel(gops); |
@@ -2140,4 +2145,5 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
2140 | gops->fifo.trigger_mmu_fault = gk20a_fifo_trigger_mmu_fault; | 2145 | gops->fifo.trigger_mmu_fault = gk20a_fifo_trigger_mmu_fault; |
2141 | gops->fifo.apply_pb_timeout = gk20a_fifo_apply_pb_timeout; | 2146 | gops->fifo.apply_pb_timeout = gk20a_fifo_apply_pb_timeout; |
2142 | gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; | 2147 | gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; |
2148 | gops->fifo.get_num_fifos = gk20a_fifo_get_num_fifos; | ||
2143 | } | 2149 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 83c4e147..ae640277 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -189,6 +189,7 @@ struct gpu_ops { | |||
189 | unsigned long engine_ids); | 189 | unsigned long engine_ids); |
190 | void (*apply_pb_timeout)(struct gk20a *g); | 190 | void (*apply_pb_timeout)(struct gk20a *g); |
191 | int (*wait_engine_idle)(struct gk20a *g); | 191 | int (*wait_engine_idle)(struct gk20a *g); |
192 | u32 (*get_num_fifos)(struct gk20a *g); | ||
192 | } fifo; | 193 | } fifo; |
193 | struct pmu_v { | 194 | struct pmu_v { |
194 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 195 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 86d049cf..cdc8c810 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -99,6 +99,11 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | |||
99 | gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0); | 99 | gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0); |
100 | } | 100 | } |
101 | 101 | ||
102 | static u32 gm20b_fifo_get_num_fifos(struct gk20a *g) | ||
103 | { | ||
104 | return ccsr_channel__size_1_v(); | ||
105 | } | ||
106 | |||
102 | void gm20b_init_fifo(struct gpu_ops *gops) | 107 | void gm20b_init_fifo(struct gpu_ops *gops) |
103 | { | 108 | { |
104 | gops->fifo.bind_channel = channel_gm20b_bind; | 109 | gops->fifo.bind_channel = channel_gm20b_bind; |
@@ -112,4 +117,5 @@ void gm20b_init_fifo(struct gpu_ops *gops) | |||
112 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; | 117 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; |
113 | gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault; | 118 | gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault; |
114 | gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; | 119 | gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; |
120 | gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos; | ||
115 | } | 121 | } |