diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-03-25 13:50:05 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 22:02:57 -0400 |
commit | cc992500a0b2c46a72ae0618b1be57ad3ef88aab (patch) | |
tree | e3f506351d65f93bfdfd543e2ad29a2a2bbca8e2 /drivers/gpu/nvgpu | |
parent | 29ceb36331b21940afd210c594fd07e6c7337793 (diff) |
gpu: nvgpu: Regenerate HW headers
Added fuse for FBP and DS exception register.
Change-Id: Ie38a84eac40ca2d8cf3ac8f19ed6bad0d6bc1dd9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/722846
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 4 |
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h index 729d6541..a36709e3 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h | |||
@@ -118,4 +118,12 @@ static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) | |||
118 | { | 118 | { |
119 | return 0x00021d70 + i*4; | 119 | return 0x00021d70 + i*4; |
120 | } | 120 | } |
121 | static inline u32 fuse_status_opt_fbp_r(void) | ||
122 | { | ||
123 | return 0x00021d38; | ||
124 | } | ||
125 | static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) | ||
126 | { | ||
127 | return (r >> (0 + i*0)) & 0x1; | ||
128 | } | ||
121 | #endif | 129 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 11605deb..2fea4e8c 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -170,6 +170,10 @@ static inline u32 gr_exception_memfmt_m(void) | |||
170 | { | 170 | { |
171 | return 0x1 << 1; | 171 | return 0x1 << 1; |
172 | } | 172 | } |
173 | static inline u32 gr_exception_ds_m(void) | ||
174 | { | ||
175 | return 0x1 << 4; | ||
176 | } | ||
173 | static inline u32 gr_exception1_r(void) | 177 | static inline u32 gr_exception1_r(void) |
174 | { | 178 | { |
175 | return 0x00400118; | 179 | return 0x00400118; |