diff options
author | sujeet baranwal <sbaranwal@nvidia.com> | 2015-05-19 13:50:09 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-06-06 10:24:26 -0400 |
commit | cb28a538cfbec71b441b29290166c114145d6d60 (patch) | |
tree | 380df8369ebd4e0482e3b5352f7c2bd91f21e47f /drivers/gpu/nvgpu | |
parent | 0dc66952e4df80b45c77bdbb31ce2a32f216328f (diff) |
gpu: nvgpu: Alignment of data for 64 bit read
The packaging of register's value in 64 bit variable
needs the reversal of 32-bit-word.
Bug 200083334
Change-Id: Id938f2a2fcffc90ef135ae963ae288c9a655069a
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/744455
(cherry picked from commit dfd3a752ea6a0943be499410010a176756221593)
Reviewed-on: http://git-master/r/753277
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index c228b237..d73eae86 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -436,16 +436,16 @@ static int nvgpu_gpu_ioctl_wait_for_pause( | |||
436 | } | 436 | } |
437 | 437 | ||
438 | /* 64 bit read */ | 438 | /* 64 bit read */ |
439 | warps_valid = (u64)gk20a_readl(g, gr_gpc0_tpc0_sm_warp_valid_mask_r() + reg_offset) << 32; | 439 | warps_valid = (u64)gk20a_readl(g, gr_gpc0_tpc0_sm_warp_valid_mask_r() + reg_offset + 4) << 32; |
440 | warps_valid |= gk20a_readl(g, gr_gpc0_tpc0_sm_warp_valid_mask_r() + reg_offset + 4); | 440 | warps_valid |= gk20a_readl(g, gr_gpc0_tpc0_sm_warp_valid_mask_r() + reg_offset); |
441 | 441 | ||
442 | /* 64 bit read */ | 442 | /* 64 bit read */ |
443 | warps_paused = (u64)gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r() + reg_offset) << 32; | 443 | warps_paused = (u64)gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r() + reg_offset + 4) << 32; |
444 | warps_paused |= gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r() + reg_offset + 4); | 444 | warps_paused |= gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r() + reg_offset); |
445 | 445 | ||
446 | /* 64 bit read */ | 446 | /* 64 bit read */ |
447 | warps_trapped = (u64)gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r() + reg_offset) << 32; | 447 | warps_trapped = (u64)gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r() + reg_offset + 4) << 32; |
448 | warps_trapped |= gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r() + reg_offset + 4); | 448 | warps_trapped |= gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r() + reg_offset); |
449 | 449 | ||
450 | w_state[sm_id].valid_warps = warps_valid; | 450 | w_state[sm_id].valid_warps = warps_valid; |
451 | w_state[sm_id].trapped_warps = warps_trapped; | 451 | w_state[sm_id].trapped_warps = warps_trapped; |