diff options
author | Sai Nikhil <snikhil@nvidia.com> | 2018-09-11 01:08:54 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-27 02:35:37 -0400 |
commit | c6cfb12d91accc759ed80985573014df89d9cdaa (patch) | |
tree | 0bc9f467e0f52732a9d5916cb804b12b8f00134b /drivers/gpu/nvgpu | |
parent | c18c8b5b28b839ac20ae2c4b1003e9b44199016a (diff) |
gpu: nvgpu: pmgr: fix MISRA Rule 10.4 Violations
MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Id3b2c8ea1af1807087468c6978abfbfc85bee2ec
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809757
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/boardobj/boardobjgrp.h | 58 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlpmgr.h | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pmgrpmu.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrdev.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrmonitor.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrpolicy.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrpolicy.h | 2 |
7 files changed, 55 insertions, 55 deletions
diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp.h b/drivers/gpu/nvgpu/boardobj/boardobjgrp.h index e9df445f..cd13b85e 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobjgrp.h +++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp.h | |||
@@ -234,17 +234,17 @@ struct boardobjgrp { | |||
234 | * be inserted contiguously (i.e. w/o fear of colliding with existing objects). | 234 | * be inserted contiguously (i.e. w/o fear of colliding with existing objects). |
235 | */ | 235 | */ |
236 | #define BOARDOBJGRP_NEXT_EMPTY_IDX(_pboardobjgrp) \ | 236 | #define BOARDOBJGRP_NEXT_EMPTY_IDX(_pboardobjgrp) \ |
237 | ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0 : \ | 237 | ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0U : \ |
238 | ((((_pboardobjgrp)->objmaxidx + 1) >= (_pboardobjgrp)->objslots) ? \ | 238 | ((((_pboardobjgrp)->objmaxidx + 1U) >= (_pboardobjgrp)->objslots) ? \ |
239 | (u8)CTRL_BOARDOBJ_IDX_INVALID : (u8)((_pboardobjgrp)->objmaxidx + 1))) | 239 | (u8)CTRL_BOARDOBJ_IDX_INVALID : (u8)((_pboardobjgrp)->objmaxidx + 1U))) |
240 | 240 | ||
241 | /* | 241 | /* |
242 | * Helper macro to determine the number of @ref BOARDOBJ pointers | 242 | * Helper macro to determine the number of @ref BOARDOBJ pointers |
243 | * that are required to be allocated in PMU @ref ppObjects. | 243 | * that are required to be allocated in PMU @ref ppObjects. |
244 | */ | 244 | */ |
245 | #define BOARDOBJGRP_PMU_SLOTS_GET(_pboardobjgrp) \ | 245 | #define BOARDOBJGRP_PMU_SLOTS_GET(_pboardobjgrp) \ |
246 | ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0 : \ | 246 | ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0U : \ |
247 | (u8)((_pboardobjgrp)->objmaxidx + 1)) | 247 | (u8)((_pboardobjgrp)->objmaxidx + 1U)) |
248 | 248 | ||
249 | #define BOARDOBJGRP_OBJ_GET_BY_IDX(_pboardobjgrp, _idx) \ | 249 | #define BOARDOBJGRP_OBJ_GET_BY_IDX(_pboardobjgrp, _idx) \ |
250 | ((_pboardobjgrp)->objgetbyidx((_pboardobjgrp), (_idx))) | 250 | ((_pboardobjgrp)->objgetbyidx((_pboardobjgrp), (_idx))) |
@@ -274,8 +274,8 @@ struct boardobjgrp { | |||
274 | #define BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(mask_width, index, mask) \ | 274 | #define BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(mask_width, index, mask) \ |
275 | { \ | 275 | { \ |
276 | u##mask_width lcl_msk = (u##mask_width)(mask); \ | 276 | u##mask_width lcl_msk = (u##mask_width)(mask); \ |
277 | for (index = 0; lcl_msk != 0; index++, lcl_msk >>= 1) { \ | 277 | for (index = 0; lcl_msk != 0U; index++, lcl_msk >>= 1U) { \ |
278 | if (((u##mask_width)((u64)1) & lcl_msk) == 0) { \ | 278 | if (((u##mask_width)((u64)1) & lcl_msk) == 0U) { \ |
279 | continue; \ | 279 | continue; \ |
280 | } | 280 | } |
281 | 281 | ||
@@ -289,22 +289,22 @@ struct boardobjgrp { | |||
289 | * @ref BOARDOBJGRP::unitId and, thus, certain BOARDOBJGRP PMU interfaces are | 289 | * @ref BOARDOBJGRP::unitId and, thus, certain BOARDOBJGRP PMU interfaces are |
290 | * not supported. | 290 | * not supported. |
291 | */ | 291 | */ |
292 | #define BOARDOBJGRP_UNIT_ID_INVALID 255 | 292 | #define BOARDOBJGRP_UNIT_ID_INVALID 255U |
293 | 293 | ||
294 | /*! | 294 | /*! |
295 | * Invalid UNIT_ID. Used to indicate that the implementing class has not set | 295 | * Invalid UNIT_ID. Used to indicate that the implementing class has not set |
296 | * @ref BOARDOBJGRP::grpType and, thus, certain BOARDOBJGRP PMU interfaces are | 296 | * @ref BOARDOBJGRP::grpType and, thus, certain BOARDOBJGRP PMU interfaces are |
297 | * not supported. | 297 | * not supported. |
298 | */ | 298 | */ |
299 | #define BOARDOBJGRP_GRP_CLASS_ID_INVALID 255 | 299 | #define BOARDOBJGRP_GRP_CLASS_ID_INVALID 255U |
300 | 300 | ||
301 | /*! | 301 | /*! |
302 | * Invalid UNIT_ID. Used to indicate that the implementing class has not set | 302 | * Invalid UNIT_ID. Used to indicate that the implementing class has not set |
303 | * @ref BOARDOBJGRP::grpSetCmdId and, thus, certain BOARDOBJGRP PMU interfaces | 303 | * @ref BOARDOBJGRP::grpSetCmdId and, thus, certain BOARDOBJGRP PMU interfaces |
304 | * are not supported. | 304 | * are not supported. |
305 | */ | 305 | */ |
306 | #define BOARDOBJGRP_GRP_CMD_ID_INVALID 255 | 306 | #define BOARDOBJGRP_GRP_CMD_ID_INVALID 255U |
307 | #define BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID 255 | 307 | #define BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID 255U |
308 | 308 | ||
309 | /*! | 309 | /*! |
310 | * Helper macro to construct a BOARDOBJGRP's PMU SW state. | 310 | * Helper macro to construct a BOARDOBJGRP's PMU SW state. |
@@ -379,14 +379,14 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask); | |||
379 | 379 | ||
380 | #define HIGHESTBITIDX_32(n32) \ | 380 | #define HIGHESTBITIDX_32(n32) \ |
381 | { \ | 381 | { \ |
382 | u32 count = 0; \ | 382 | u32 count = 0U; \ |
383 | while (n32 >>= 1) { \ | 383 | while (n32 >>= 1U) { \ |
384 | count++; \ | 384 | count++; \ |
385 | } \ | 385 | } \ |
386 | n32 = count; \ | 386 | n32 = count; \ |
387 | } | 387 | } |
388 | 388 | ||
389 | #define LOWESTBIT(x) ((x) & (((x)-1) ^ (x))) | 389 | #define LOWESTBIT(x) ((x) & (((x)-1U) ^ (x))) |
390 | 390 | ||
391 | #define HIGHESTBIT(n32) \ | 391 | #define HIGHESTBIT(n32) \ |
392 | { \ | 392 | { \ |
@@ -394,7 +394,7 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask); | |||
394 | n32 = NVBIT(n32); \ | 394 | n32 = NVBIT(n32); \ |
395 | } | 395 | } |
396 | 396 | ||
397 | #define ONEBITSET(x) ((x) && (((x) & ((x)-1)) == 0)) | 397 | #define ONEBITSET(x) ((x) && (((x) & ((x)-1U)) == 0U)) |
398 | 398 | ||
399 | #define LOWESTBITIDX_32(n32) \ | 399 | #define LOWESTBITIDX_32(n32) \ |
400 | { \ | 400 | { \ |
@@ -404,24 +404,24 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask); | |||
404 | 404 | ||
405 | #define NUMSETBITS_32(n32) \ | 405 | #define NUMSETBITS_32(n32) \ |
406 | { \ | 406 | { \ |
407 | n32 = n32 - ((n32 >> 1) & 0x55555555); \ | 407 | n32 = n32 - ((n32 >> 1U) & 0x55555555U); \ |
408 | n32 = (n32 & 0x33333333) + ((n32 >> 2) & 0x33333333); \ | 408 | n32 = (n32 & 0x33333333U) + ((n32 >> 2U) & 0x33333333U); \ |
409 | n32 = (((n32 + (n32 >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24; \ | 409 | n32 = (((n32 + (n32 >> 4U)) & 0x0F0F0F0FU) * 0x01010101U) >> 24U; \ |
410 | } | 410 | } |
411 | 411 | ||
412 | #define IDX_32(n32) \ | 412 | #define IDX_32(n32) \ |
413 | { \ | 413 | { \ |
414 | u32 idx = 0; \ | 414 | u32 idx = 0U; \ |
415 | if ((n32) & 0xFFFF0000) \ | 415 | if ((n32) & 0xFFFF0000U) \ |
416 | idx += 16; \ | 416 | idx += 16U; \ |
417 | if ((n32) & 0xFF00FF00) \ | 417 | if ((n32) & 0xFF00FF00U) \ |
418 | idx += 8; \ | 418 | idx += 8U; \ |
419 | if ((n32) & 0xF0F0F0F0) \ | 419 | if ((n32) & 0xF0F0F0F0U) \ |
420 | idx += 4; \ | 420 | idx += 4U; \ |
421 | if ((n32) & 0xCCCCCCCC) \ | 421 | if ((n32) & 0xCCCCCCCCU) \ |
422 | idx += 2; \ | 422 | idx += 2U; \ |
423 | if ((n32) & 0xAAAAAAAA) \ | 423 | if ((n32) & 0xAAAAAAAAU) \ |
424 | idx += 1; \ | 424 | idx += 1U; \ |
425 | (n32) = idx; \ | 425 | (n32) = idx; \ |
426 | } | 426 | } |
427 | 427 | ||
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h b/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h index 165bbd5d..90f6501b 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h | |||
@@ -27,23 +27,23 @@ | |||
27 | #include "ctrlboardobj.h" | 27 | #include "ctrlboardobj.h" |
28 | 28 | ||
29 | /* valid power domain values */ | 29 | /* valid power domain values */ |
30 | #define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32 | 30 | #define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32U |
31 | #define CTRL_PMGR_PWR_VIOLATION_MAX 0x06 | 31 | #define CTRL_PMGR_PWR_VIOLATION_MAX 0x06U |
32 | 32 | ||
33 | #define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221 0x4E | 33 | #define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221 0x4EU |
34 | 34 | ||
35 | #define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID 0xFF | 35 | #define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID 0xFFU |
36 | #define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR 0x08 | 36 | #define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR 0x08U |
37 | 37 | ||
38 | #define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X 0x30 | 38 | #define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X 0x30U |
39 | #define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD 0x04 | 39 | #define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD 0x04U |
40 | #define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD 0x0C | 40 | #define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD 0x0CU |
41 | 41 | ||
42 | #define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS 0x8 | 42 | #define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS 0x8U |
43 | #define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES 0x08 | 43 | #define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES 0x08U |
44 | #define CTRL_PMGR_PWR_POLICY_INDEX_INVALID 0xFF | 44 | #define CTRL_PMGR_PWR_POLICY_INDEX_INVALID 0xFFU |
45 | #define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM 0xFE | 45 | #define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM 0xFEU |
46 | #define CTRL_PMGR_PWR_POLICY_LIMIT_MAX (0xFFFFFFFF) | 46 | #define CTRL_PMGR_PWR_POLICY_LIMIT_MAX (0xFFFFFFFFU) |
47 | 47 | ||
48 | struct ctrl_pmgr_pwr_device_info_rshunt { | 48 | struct ctrl_pmgr_pwr_device_info_rshunt { |
49 | bool use_fxp8_8; | 49 | bool use_fxp8_8; |
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c index 411550be..b6947f20 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c | |||
@@ -52,7 +52,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | |||
52 | 52 | ||
53 | if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_SET_OBJECT) { | 53 | if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_SET_OBJECT) { |
54 | if ((msg->msg.pmgr.set_object.b_success != 1) || | 54 | if ((msg->msg.pmgr.set_object.b_success != 1) || |
55 | (msg->msg.pmgr.set_object.flcnstatus != 0) ) { | 55 | (msg->msg.pmgr.set_object.flcnstatus != 0U)) { |
56 | nvgpu_err(g, "pmgr msg failed %x %x %x %x", | 56 | nvgpu_err(g, "pmgr msg failed %x %x %x %x", |
57 | msg->msg.pmgr.set_object.msg_type, | 57 | msg->msg.pmgr.set_object.msg_type, |
58 | msg->msg.pmgr.set_object.b_success, | 58 | msg->msg.pmgr.set_object.b_success, |
@@ -62,7 +62,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | |||
62 | } | 62 | } |
63 | } else if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_QUERY) { | 63 | } else if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_QUERY) { |
64 | if ((msg->msg.pmgr.query.b_success != 1) || | 64 | if ((msg->msg.pmgr.query.b_success != 1) || |
65 | (msg->msg.pmgr.query.flcnstatus != 0) ) { | 65 | (msg->msg.pmgr.query.flcnstatus != 0U)) { |
66 | nvgpu_err(g, "pmgr msg failed %x %x %x %x", | 66 | nvgpu_err(g, "pmgr msg failed %x %x %x %x", |
67 | msg->msg.pmgr.query.msg_type, | 67 | msg->msg.pmgr.query.msg_type, |
68 | msg->msg.pmgr.query.b_success, | 68 | msg->msg.pmgr.query.b_success, |
@@ -72,7 +72,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | |||
72 | } | 72 | } |
73 | } else if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_LOAD) { | 73 | } else if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_LOAD) { |
74 | if ((msg->msg.pmgr.query.b_success != 1) || | 74 | if ((msg->msg.pmgr.query.b_success != 1) || |
75 | (msg->msg.pmgr.query.flcnstatus != 0) ) { | 75 | (msg->msg.pmgr.query.flcnstatus != 0U)) { |
76 | nvgpu_err(g, "pmgr msg failed %x %x %x", | 76 | nvgpu_err(g, "pmgr msg failed %x %x %x", |
77 | msg->msg.pmgr.load.msg_type, | 77 | msg->msg.pmgr.load.msg_type, |
78 | msg->msg.pmgr.load.b_success, | 78 | msg->msg.pmgr.load.b_success, |
@@ -133,7 +133,7 @@ static u32 pmgr_pmu_set_object(struct gk20a *g, | |||
133 | gk20a_get_gr_idle_timeout(g), | 133 | gk20a_get_gr_idle_timeout(g), |
134 | &handlerparams.success, 1); | 134 | &handlerparams.success, 1); |
135 | 135 | ||
136 | if (handlerparams.success == 0) { | 136 | if (handlerparams.success == 0U) { |
137 | nvgpu_err(g, "could not process cmd"); | 137 | nvgpu_err(g, "could not process cmd"); |
138 | status = -ETIMEDOUT; | 138 | status = -ETIMEDOUT; |
139 | goto exit; | 139 | goto exit; |
@@ -431,7 +431,7 @@ u32 pmgr_pmu_pwr_devices_query_blocking( | |||
431 | gk20a_get_gr_idle_timeout(g), | 431 | gk20a_get_gr_idle_timeout(g), |
432 | &handlerparams.success, 1); | 432 | &handlerparams.success, 1); |
433 | 433 | ||
434 | if (handlerparams.success == 0) { | 434 | if (handlerparams.success == 0U) { |
435 | nvgpu_err(g, "could not process cmd"); | 435 | nvgpu_err(g, "could not process cmd"); |
436 | status = -ETIMEDOUT; | 436 | status = -ETIMEDOUT; |
437 | goto exit; | 437 | goto exit; |
@@ -475,7 +475,7 @@ static u32 pmgr_pmu_load_blocking(struct gk20a *g) | |||
475 | gk20a_get_gr_idle_timeout(g), | 475 | gk20a_get_gr_idle_timeout(g), |
476 | &handlerparams.success, 1); | 476 | &handlerparams.success, 1); |
477 | 477 | ||
478 | if (handlerparams.success == 0) { | 478 | if (handlerparams.success == 0U) { |
479 | nvgpu_err(g, "could not process cmd"); | 479 | nvgpu_err(g, "could not process cmd"); |
480 | status = -ETIMEDOUT; | 480 | status = -ETIMEDOUT; |
481 | goto exit; | 481 | goto exit; |
diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c index cf45f723..c1bf0844 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrdev.c +++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c | |||
@@ -40,7 +40,7 @@ static int _pwr_device_pmudata_instget(struct gk20a *g, | |||
40 | 40 | ||
41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
42 | if (((u32)BIT(idx) & | 42 | if (((u32)BIT(idx) & |
43 | ppmgrdevice->hdr.data.super.obj_mask.super.data[0]) == 0) { | 43 | ppmgrdevice->hdr.data.super.obj_mask.super.data[0]) == 0U) { |
44 | return -EINVAL; | 44 | return -EINVAL; |
45 | } | 45 | } |
46 | 46 | ||
@@ -191,7 +191,7 @@ static int devinit_get_pwr_device_table(struct gk20a *g, | |||
191 | 191 | ||
192 | memcpy(&pwr_sensor_table_entry.class_param0, | 192 | memcpy(&pwr_sensor_table_entry.class_param0, |
193 | (curr_pwr_device_table_ptr + 1), | 193 | (curr_pwr_device_table_ptr + 1), |
194 | (VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 - 1)); | 194 | (VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 - 1U)); |
195 | 195 | ||
196 | device_type = (u8)BIOS_GET_FIELD( | 196 | device_type = (u8)BIOS_GET_FIELD( |
197 | pwr_sensor_table_entry.flags0, | 197 | pwr_sensor_table_entry.flags0, |
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c index 28074afb..710ae85b 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c +++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c | |||
@@ -40,7 +40,7 @@ static int _pwr_channel_pmudata_instget(struct gk20a *g, | |||
40 | 40 | ||
41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
42 | if (((u32)BIT(idx) & | 42 | if (((u32)BIT(idx) & |
43 | ppmgrchannel->hdr.data.super.obj_mask.super.data[0]) == 0) { | 43 | ppmgrchannel->hdr.data.super.obj_mask.super.data[0]) == 0U) { |
44 | return -EINVAL; | 44 | return -EINVAL; |
45 | } | 45 | } |
46 | 46 | ||
@@ -67,7 +67,7 @@ static int _pwr_channel_rels_pmudata_instget(struct gk20a *g, | |||
67 | 67 | ||
68 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 68 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
69 | if (((u32)BIT(idx) & | 69 | if (((u32)BIT(idx) & |
70 | ppmgrchrels->hdr.data.super.obj_mask.super.data[0]) == 0) { | 70 | ppmgrchrels->hdr.data.super.obj_mask.super.data[0]) == 0U) { |
71 | return -EINVAL; | 71 | return -EINVAL; |
72 | } | 72 | } |
73 | 73 | ||
@@ -241,7 +241,7 @@ static int devinit_get_pwr_topology_table(struct gk20a *g, | |||
241 | 241 | ||
242 | memcpy(&pwr_topology_table_entry.param0, | 242 | memcpy(&pwr_topology_table_entry.param0, |
243 | (curr_pwr_topology_table_ptr + 2), | 243 | (curr_pwr_topology_table_ptr + 2), |
244 | (VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 - 2)); | 244 | (VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 - 2U)); |
245 | 245 | ||
246 | class_type = (u8)BIOS_GET_FIELD( | 246 | class_type = (u8)BIOS_GET_FIELD( |
247 | pwr_topology_table_entry.flags0, | 247 | pwr_topology_table_entry.flags0, |
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c index 82cf0e78..3bf6f328 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c | |||
@@ -338,7 +338,7 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g, | |||
338 | pwrpolicy, | 338 | pwrpolicy, |
339 | PWR_POLICY_LIMIT_ID_BATT, | 339 | PWR_POLICY_LIMIT_ID_BATT, |
340 | CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM, | 340 | CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM, |
341 | ((pwrpolicyparams->limit_batt != 0) ? | 341 | ((pwrpolicyparams->limit_batt != 0U) ? |
342 | pwrpolicyparams->limit_batt: | 342 | pwrpolicyparams->limit_batt: |
343 | CTRL_PMGR_PWR_POLICY_LIMIT_MAX)); | 343 | CTRL_PMGR_PWR_POLICY_LIMIT_MAX)); |
344 | 344 | ||
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h index 868bc2cb..74f4937d 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h | |||
@@ -29,7 +29,7 @@ | |||
29 | #include "boardobj/boardobj.h" | 29 | #include "boardobj/boardobj.h" |
30 | #include "ctrl/ctrlpmgr.h" | 30 | #include "ctrl/ctrlpmgr.h" |
31 | 31 | ||
32 | #define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4 | 32 | #define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4U |
33 | 33 | ||
34 | enum pwr_policy_limit_id { | 34 | enum pwr_policy_limit_id { |
35 | PWR_POLICY_LIMIT_ID_MIN = 0x00000000, | 35 | PWR_POLICY_LIMIT_ID_MIN = 0x00000000, |