gpu: nvgpu: check engine ctx_status in wait_idle

We have following bug where GPU Host reports non-idle
when it should report engine idle

- if a context is preempted off the GPU, and there is
  no other context to load, NV_PGRAPH_ENGINE_STATUS
  will not be idle until new context is loaded

- this could cause gr_gk20a_wait_idle() to fail since
  here we rely only on NV_PGRAPH_ENGINE_STATUS to
  decide if engine is busy or not

To fix this, first check if context is valid or not
from NV_PFIFO_ENGINE_STATUS_CTX_STATUS

If context is invalid, return immediately
Otherwise, continue as before

Also, add accessors for invalid ctx_status

Bug 1826768

Change-Id: Id627be3f02e79f4beac59a8b5195d08eabf651f2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1237521
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 24 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 1a93d546..fc1978ed 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -330,6 +330,8 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long end_jiffies,
         bool ctxsw_active;
         bool gr_busy;
         u32 gr_engine_id;
+        u32 engine_status;
+        bool ctx_status_invalid;
 
         gk20a_dbg_fn("");
 
@@ -343,14 +345,21 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long end_jiffies,
                 gr_enabled = gk20a_readl(g, mc_enable_r()) &
                         mc_enable_pgraph_enabled_f();
 
-                ctxsw_active = gk20a_readl(g,
-                        fifo_engine_status_r(gr_engine_id)) &
+                engine_status = gk20a_readl(g,
+                                        fifo_engine_status_r(gr_engine_id));
+
+                ctxsw_active = engine_status &
                         fifo_engine_status_ctxsw_in_progress_f();
 
+                ctx_status_invalid =
+                        (fifo_engine_status_ctx_status_v(engine_status) ==
+                         fifo_engine_status_ctx_status_invalid_v());
+
                 gr_busy = gk20a_readl(g, gr_engine_status_r()) &
                         gr_engine_status_value_busy_f();
 
-                if (!gr_enabled || (!gr_busy && !ctxsw_active)) {
+                if (!gr_enabled || ctx_status_invalid
+                                || (!gr_busy && !ctxsw_active)) {
                         gk20a_dbg_fn("done");
                         return 0;
                 }
diff --git a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
index c5c95cdf..4d54c89f 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
@@ -478,6 +478,10 @@ static inline u32 fifo_engine_status_ctx_status_v(u32 r)
 {
         return (r >> 13) & 0x7;
 }
+static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
+{
+        return 0x00000000;
+}
 static inline u32 fifo_engine_status_ctx_status_valid_v(void)
 {
         return 0x00000001;
diff --git a/drivers/gpu/nvgpu/gm206/hw_fifo_gm206.h b/drivers/gpu/nvgpu/gm206/hw_fifo_gm206.h
index 56654124..19148b03 100644
--- a/drivers/gpu/nvgpu/gm206/hw_fifo_gm206.h
+++ b/drivers/gpu/nvgpu/gm206/hw_fifo_gm206.h
@@ -426,6 +426,10 @@ static inline u32 fifo_engine_status_ctx_status_v(u32 r)
 {
         return (r >> 13) & 0x7;
 }
+static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
+{
+        return 0x00000000;
+}
 static inline u32 fifo_engine_status_ctx_status_valid_v(void)
 {
         return 0x00000001;
diff --git a/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h
index 01e01695..964f4bf9 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h
@@ -430,6 +430,10 @@ static inline u32 fifo_engine_status_ctx_status_v(u32 r)
 {
         return (r >> 13) & 0x7;
 }
+static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
+{
+        return 0x00000000;
+}
 static inline u32 fifo_engine_status_ctx_status_valid_v(void)
 {
         return 0x00000001;