gpu: nvgpu: correct NUM_FBPAS

Although igpu does not have an FBPA unit, the hardware reports one, and
the ucode leaves space for one in the HWPM context save buffer. So
let NUM_FBPAS reflect this, so that registers that follow this section
in the context buffer are offset properly

JIRA EVLR-1716

Change-Id: I067d5ec3afd356bcb4270fc2b5d12daef2ce3944
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1535274
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 6 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 521cafa3..4b64d44d 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -151,11 +151,14 @@ static int gv11b_get_litter_value(struct gk20a *g, int value)
         case GPU_LIT_SM_PRI_STRIDE:
                 ret = proj_sm_stride_v();
                 break;
-        /* GV11B does not have a FBPA unit, despite what's listed in the
-         * hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS,
-         * so hardcode all values to 0.
+        /* Even though GV11B doesn't have an FBPA unit, the HW reports one,
+         * and the microcode as a result leaves space in the context buffer
+         * for one, so make sure SW accounts for this also.
          */
         case GPU_LIT_NUM_FBPAS:
+                ret = proj_scal_litter_num_fbpas_v();
+                break;
+        /* Hardcode FBPA values other than NUM_FBPAS to 0. */
         case GPU_LIT_FBPA_STRIDE:
         case GPU_LIT_FBPA_BASE:
         case GPU_LIT_FBPA_SHARED_BASE: