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authorSeema Khowala <seemaj@nvidia.com>2017-06-28 14:18:09 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-02 13:20:21 -0400
commitb61a3951065ba6fa57b492c563c1681136bf69bf (patch)
tree6c8dae848fa2935d6a66cf8e640abb957aa8e9bb /drivers/gpu/nvgpu
parenteabf3541ea8dc91689240e3ba367487fa880b5e0 (diff)
gpu: nvgpu: gp10b_ce_isr declared non-static
Required for t19x ce isr handling JIRA GPUT19X-46 JIRA GPUT19X-12 Change-Id: I18558d633012205f7e0920da65c8d9e89aab906d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1510290 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/gp10b/ce_gp10b.c2
-rw-r--r--drivers/gpu/nvgpu/gp10b/ce_gp10b.h1
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
index 169309fa..1fff37fb 100644
--- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
@@ -36,7 +36,7 @@ static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr)
36 return ce_intr_status_launcherr_pending_f(); 36 return ce_intr_status_launcherr_pending_f();
37} 37}
38 38
39static void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) 39void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
40{ 40{
41 u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); 41 u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
42 u32 clear_intr = 0; 42 u32 clear_intr = 0;
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
index 948d0454..134c2ddb 100644
--- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
@@ -22,5 +22,6 @@
22#include "gk20a/tsg_gk20a.h" 22#include "gk20a/tsg_gk20a.h"
23 23
24void gp10b_init_ce(struct gpu_ops *gops); 24void gp10b_init_ce(struct gpu_ops *gops);
25void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
25 26
26#endif /*__CE2_GP10B_H__*/ 27#endif /*__CE2_GP10B_H__*/