diff options
author | Alex Frid <afrid@nvidia.com> | 2014-09-16 19:44:43 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:41 -0400 |
commit | b318d4c407dda213961255fe3bcff8a2705d0abc (patch) | |
tree | f11d1e3211ea47642d2590f56aad57896c82fbcb /drivers/gpu/nvgpu | |
parent | 7d4a4a7da688bcbdd4b76b5641c8e161676c8ba0 (diff) |
gpu: nvgpu: Override GM20b RAM SVOP PDP fuses
Override GM20b RAM SVOP PDP fuses with 0x2 setting during clock
initialization.
Bug 1550997
Change-Id: I9a873b892a2db4af384a9a7af4470562cdcb1572
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499554
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index eb7703bd..568d4dde 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include "hw_trim_gm20b.h" | 28 | #include "hw_trim_gm20b.h" |
29 | #include "hw_timer_gm20b.h" | 29 | #include "hw_timer_gm20b.h" |
30 | #include "hw_therm_gm20b.h" | 30 | #include "hw_therm_gm20b.h" |
31 | #include "hw_fuse_gm20b.h" | ||
31 | #include "clk_gm20b.h" | 32 | #include "clk_gm20b.h" |
32 | 33 | ||
33 | #define ALLOW_NON_CALIBRATED_NA_MODE 1 | 34 | #define ALLOW_NON_CALIBRATED_NA_MODE 1 |
@@ -1167,6 +1168,19 @@ static int gm20b_init_clk_setup_hw(struct gk20a *g) | |||
1167 | trim_sys_bypassctrl_gpcpll_vco_f()); | 1168 | trim_sys_bypassctrl_gpcpll_vco_f()); |
1168 | gk20a_writel(g, trim_sys_bypassctrl_r(), data); | 1169 | gk20a_writel(g, trim_sys_bypassctrl_r(), data); |
1169 | 1170 | ||
1171 | /* If not fused, set RAM SVOP PDP data 0x2, and enable fuse override */ | ||
1172 | data = gk20a_readl(g, fuse_ctrl_opt_ram_svop_pdp_r()); | ||
1173 | if (!fuse_ctrl_opt_ram_svop_pdp_data_v(data)) { | ||
1174 | data = set_field(data, fuse_ctrl_opt_ram_svop_pdp_data_m(), | ||
1175 | fuse_ctrl_opt_ram_svop_pdp_data_f(0x2)); | ||
1176 | gk20a_writel(g, fuse_ctrl_opt_ram_svop_pdp_r(), data); | ||
1177 | data = gk20a_readl(g, fuse_ctrl_opt_ram_svop_pdp_override_r()); | ||
1178 | data = set_field(data, | ||
1179 | fuse_ctrl_opt_ram_svop_pdp_override_data_m(), | ||
1180 | fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f()); | ||
1181 | gk20a_writel(g, fuse_ctrl_opt_ram_svop_pdp_override_r(), data); | ||
1182 | } | ||
1183 | |||
1170 | /* Disable idle slow down */ | 1184 | /* Disable idle slow down */ |
1171 | data = gk20a_readl(g, therm_clk_slowdown_r(0)); | 1185 | data = gk20a_readl(g, therm_clk_slowdown_r(0)); |
1172 | data = set_field(data, therm_clk_slowdown_idle_factor_m(), | 1186 | data = set_field(data, therm_clk_slowdown_idle_factor_m(), |