gpu: nvgpu: gv11b: fifo ops get_mmu_fault_info set to NULL

mmu fault h/w registers are no longer inside fifo module

JIRA GPUT19X-7
JIRA GPUT19X-12

Change-Id: I7d166f0e80cee7c040289b13a053ff2cdb7d8727
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1487327
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index 4b4c97b4..38a402dc 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -1554,6 +1554,7 @@ void gv11b_init_fifo(struct gpu_ops *gops)
         gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v;
         gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc;
         gops->fifo.trigger_mmu_fault = NULL;
+        gops->fifo.get_mmu_fault_info = NULL;
         gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status;
         gops->fifo.dump_eng_status = gv11b_dump_eng_status;
         gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc;