gpu: nvgpu: add ioctls to get current timeslice

Add the following ioctls
- NVGPU_CHANNEL_IOCTL_GET_TIMESLICE for channel timeslice in us
- NVGPU_TSG_IOCTL_GET_TIMESLICE for TSG timeslice in us

If timeslice has not been set explicitly, ioctl returns the
default timeslice that will be used when programming the runlist
entry.

Bug 1883271

Change-Id: Ib18fdd836323b1a2d4efceb1e27d07713bd6fca5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1469040
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

11 files changed, 70 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
index 8a87e4cb..4d4d1690 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
@@ -1125,6 +1125,10 @@ long gk20a_channel_ioctl(struct file *filp,
                 gk20a_channel_trace_sched_param(
                         trace_gk20a_channel_set_timeslice, ch);
                 break;
+        case NVGPU_IOCTL_CHANNEL_GET_TIMESLICE:
+                ((struct nvgpu_timeslice_args *)buf)->timeslice_us =
+                        gk20a_channel_get_timeslice(ch);
+                break;
         case NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE:
                 if (ch->g->ops.gr.set_preemption_mode) {
                         err = gk20a_busy(ch->g);
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
index e67965e1..25805ea0 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
@@ -340,6 +340,12 @@ done:
         return err;
 }
 
+static int gk20a_tsg_ioctl_get_timeslice(struct gk20a *g,
+        struct tsg_gk20a *tsg, struct nvgpu_timeslice_args *arg)
+{
+        arg->timeslice_us = gk20a_tsg_get_timeslice(tsg);
+        return 0;
+}
 
 long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
                              unsigned long arg)
@@ -455,6 +461,12 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
                         (struct nvgpu_timeslice_args *)buf);
                 break;
                 }
+        case NVGPU_IOCTL_TSG_GET_TIMESLICE:
+                {
+                err = gk20a_tsg_ioctl_get_timeslice(g, tsg,
+                        (struct nvgpu_timeslice_args *)buf);
+                break;
+                }
 
         default:
                 nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x",
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 9e3bc05e..6cb77d67 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -146,6 +146,16 @@ int channel_gk20a_commit_va(struct channel_gk20a *c)
         return 0;
 }
 
+u32 gk20a_channel_get_timeslice(struct channel_gk20a *ch)
+{
+        struct gk20a *g = ch->g;
+
+        if (!ch->timeslice_us)
+                return g->ops.fifo.default_timeslice_us(g);
+
+        return ch->timeslice_us;
+}
+
 int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g,
                 int timeslice_period,
                 int *__timeslice_timeout, int *__timeslice_scale)
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
index bbc1a72a..d3ab9b27 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
@@ -388,6 +388,7 @@ void channel_gk20a_joblist_lock(struct channel_gk20a *c);
 void channel_gk20a_joblist_unlock(struct channel_gk20a *c);
 bool channel_gk20a_joblist_is_empty(struct channel_gk20a *c);
 
+u32 gk20a_channel_get_timeslice(struct channel_gk20a *ch);
 int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g,
                 int timeslice_period,
                 int *__timeslice_timeout, int *__timeslice_scale);
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 8085318d..f536b374 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -2920,14 +2920,24 @@ void gk20a_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
                         ram_rl_entry_timeslice_timeout_f(tsg->timeslice_timeout);
         else
                 runlist_entry_0 |=
-                        ram_rl_entry_timeslice_scale_3_f() |
-                        ram_rl_entry_timeslice_timeout_128_f();
+                        ram_rl_entry_timeslice_scale_f(
+                                NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE) |
+                        ram_rl_entry_timeslice_timeout_f(
+                                NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT);
 
         runlist[0] = runlist_entry_0;
         runlist[1] = 0;
 
 }
 
+u32 gk20a_fifo_default_timeslice_us(struct gk20a *g)
+{
+        return (((u64)(NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT <<
+                                NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE) *
+                        (u64)g->ptimer_src_freq) /
+                        (u64)PTIMER_REF_FREQ_HZ);
+}
+
 void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist)
 {
         runlist[0] = ram_rl_entry_chid_f(ch->hw_chid);
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 0bec9e82..b09fde65 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -47,6 +47,9 @@
 #define RC_TYPE_PBDMA_FAULT             2
 #define RC_TYPE_NO_RC                   0xff
 
+#define NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT    128UL
+#define NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE      3UL
+
 /*
  * Number of entries in the kickoff latency buffer, used to calculate
  * the profiling and histogram. This number is calculated to be statistically
@@ -399,4 +402,6 @@ void gk20a_fifo_reset_pbdma_method(struct gk20a *g, int pbdma_id,
                          int pbdma_method_index);
 unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id,
                         u32 pbdma_intr_0, u32 *handled, u32 *error_notifier);
+
+u32 gk20a_fifo_default_timeslice_us(struct gk20a *g);
 #endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 9ab0d202..b3292ac4 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -445,6 +445,7 @@ struct gpu_ops {
                 int (*channel_set_timeslice)(struct channel_gk20a *ch,
                                         u32 timeslice);
                 int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice);
+                u32 (*default_timeslice_us)(struct gk20a *);
                 int (*force_reset_ch)(struct channel_gk20a *ch,
                                         u32 err_code, bool verbose);
                 int (*engine_enum_from_type)(struct gk20a *g, u32 engine_type,
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
index f9884cfb..9cb5b262 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
@@ -211,6 +211,16 @@ int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
         return g->ops.fifo.tsg_set_timeslice(tsg, timeslice);
 }
 
+u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg)
+{
+        struct gk20a *g = tsg->g;
+
+        if (!tsg->timeslice_us)
+                return g->ops.fifo.default_timeslice_us(g);
+
+        return tsg->timeslice_us;
+}
+
 static void release_used_tsg(struct fifo_gk20a *f, struct tsg_gk20a *tsg)
 {
         nvgpu_mutex_acquire(&f->tsg_inuse_mutex);
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
index 945058a2..5a13c912 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
@@ -70,6 +70,7 @@ void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg,
                                        int event_id);
 int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level);
 int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
+u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg);
 int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg,
                                 u32 priority);
 
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index ed3a4b98..513f250d 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -195,6 +195,7 @@ void gm20b_init_fifo(struct gpu_ops *gops)
         gops->fifo.setup_ramfc = gk20a_fifo_setup_ramfc;
         gops->fifo.channel_set_priority = gk20a_fifo_set_priority;
         gops->fifo.channel_set_timeslice = gk20a_fifo_set_timeslice;
+        gops->fifo.default_timeslice_us = gk20a_fifo_default_timeslice_us;
         gops->fifo.setup_userd = gk20a_fifo_setup_userd;
         gops->fifo.userd_gp_get = gk20a_fifo_userd_gp_get;
         gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put;
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 309a395a..28514386 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -655,8 +655,11 @@ static int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
         p->handle = ch->virt_ctx;
         p->timeslice_us = timeslice;
         err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
-        WARN_ON(err || msg.ret);
-        return err ? err : msg.ret;
+        err = err ? err : msg.ret;
+        WARN_ON(err);
+        if (!err)
+                ch->timeslice_us = p->timeslice_us;
+        return err;
 }
 
 static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
@@ -776,6 +779,13 @@ int vgpu_fifo_nonstall_isr(struct gk20a *g,
         return 0;
 }
 
+u32 vgpu_fifo_default_timeslice_us(struct gk20a *g)
+{
+        struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
+
+        return priv->constants.default_timeslice_us;
+}
+
 void vgpu_init_fifo_ops(struct gpu_ops *gops)
 {
         gops->fifo.bind_channel = vgpu_channel_bind;
@@ -794,4 +804,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops)
         gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice;
         gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch;
         gops->fifo.init_engine_info = vgpu_fifo_init_engine_info;
+        gops->fifo.default_timeslice_us = vgpu_fifo_default_timeslice_us;
 }