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author | Deepak Nibade <dnibade@nvidia.com> | 2014-04-29 06:08:24 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:09:22 -0400 |
commit | acd6d02069b499bbaa83b7c5ba6a952e6a6fd476 (patch) | |
tree | 17c4d400eccec205a9b6568e695eb4a49969e8b9 /drivers/gpu/nvgpu | |
parent | 2a0d69b7d2024ffe8e593bc5bce35f59a1171ad2 (diff) |
gpu: nvgpu: gk20a: add fecs error intr handler
Add handler gk20a_gr_handle_fecs_error() in case we have
pending fecs error interrupt
And clear this interrupt after handling.
Also, in gk20a_gr_handle_fecs_error(), for now just print
the contents of NV_PGRAPH_FECS_INTR and clear it
Bug 1495957
Change-Id: Ie7f70c84ec76ab698141646cd683584c4501e3e0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/402874
(cherry picked from commit a29f219c57d65a06f6dae8086f19fa1af94d95bd)
Reviewed-on: http://git-master/r/403587
(cherry picked from commit e65ebebd0d4d5c3dbb6fa454dd51c383ea13d715)
Reviewed-on: http://git-master/r/411160
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 08309f0f..0cb6c933 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4854,6 +4854,22 @@ static int gk20a_gr_handle_illegal_class(struct gk20a *g, | |||
4854 | return -EINVAL; | 4854 | return -EINVAL; |
4855 | } | 4855 | } |
4856 | 4856 | ||
4857 | static int gk20a_gr_handle_fecs_error(struct gk20a *g, | ||
4858 | struct gr_isr_data *isr_data) | ||
4859 | { | ||
4860 | struct fifo_gk20a *f = &g->fifo; | ||
4861 | struct channel_gk20a *ch = &f->channel[isr_data->chid]; | ||
4862 | u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_intr_r()); | ||
4863 | gk20a_dbg_fn(""); | ||
4864 | |||
4865 | gk20a_err(dev_from_gk20a(g), | ||
4866 | "unhandled fecs error interrupt 0x%08x for channel %u", | ||
4867 | gr_fecs_intr, ch->hw_chid); | ||
4868 | |||
4869 | gk20a_writel(g, gr_fecs_intr_r(), gr_fecs_intr); | ||
4870 | return -EINVAL; | ||
4871 | } | ||
4872 | |||
4857 | static int gk20a_gr_handle_class_error(struct gk20a *g, | 4873 | static int gk20a_gr_handle_class_error(struct gk20a *g, |
4858 | struct gr_isr_data *isr_data) | 4874 | struct gr_isr_data *isr_data) |
4859 | { | 4875 | { |
@@ -5341,6 +5357,13 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5341 | gr_intr &= ~gr_intr_illegal_class_pending_f(); | 5357 | gr_intr &= ~gr_intr_illegal_class_pending_f(); |
5342 | } | 5358 | } |
5343 | 5359 | ||
5360 | if (gr_intr & gr_intr_fecs_error_pending_f()) { | ||
5361 | need_reset |= gk20a_gr_handle_fecs_error(g, &isr_data); | ||
5362 | gk20a_writel(g, gr_intr_r(), | ||
5363 | gr_intr_fecs_error_reset_f()); | ||
5364 | gr_intr &= ~gr_intr_fecs_error_pending_f(); | ||
5365 | } | ||
5366 | |||
5344 | if (gr_intr & gr_intr_class_error_pending_f()) { | 5367 | if (gr_intr & gr_intr_class_error_pending_f()) { |
5345 | need_reset |= gk20a_gr_handle_class_error(g, &isr_data); | 5368 | need_reset |= gk20a_gr_handle_class_error(g, &isr_data); |
5346 | gk20a_writel(g, gr_intr_r(), | 5369 | gk20a_writel(g, gr_intr_r(), |