diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-03-13 15:03:25 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-14 22:50:10 -0400 |
commit | a4deb1079e6617d48dc1668daeb46fa2f1c84803 (patch) | |
tree | ce6fd73fa36abddc59302af0fa544cc59c7543d0 /drivers/gpu/nvgpu | |
parent | 93ba29c5b5adae918545be75c67bc00614a7eef8 (diff) |
gpu: nvgpu: gp10b: fix stall interrupt enablement
Currently priv, pbus and ltc interrupts are enabled as non-stall but
being handled in stall isr. Fix is to configure them as stall interrupt.
Change-Id: I78a0ad3eb4207dcd70da63098234ed6139f0664a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1320031
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index abbd2191..fc0e6553 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -29,20 +29,20 @@ void mc_gp10b_intr_enable(struct gk20a *g) | |||
29 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), | 29 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), |
30 | 0xffffffff); | 30 | 0xffffffff); |
31 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = | 31 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = |
32 | mc_intr_pfifo_pending_f() | 32 | mc_intr_pfifo_pending_f() | |
33 | | mc_intr_replayable_fault_pending_f() | 33 | mc_intr_priv_ring_pending_f() | |
34 | | eng_intr_mask; | 34 | mc_intr_pbus_pending_f() | |
35 | mc_intr_ltc_pending_f() | | ||
36 | mc_intr_replayable_fault_pending_f() | | ||
37 | eng_intr_mask; | ||
35 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | 38 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), |
36 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); | 39 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); |
37 | 40 | ||
38 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | 41 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), |
39 | 0xffffffff); | 42 | 0xffffffff); |
40 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = | 43 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = |
41 | mc_intr_pfifo_pending_f() | 44 | mc_intr_pfifo_pending_f() | |
42 | | mc_intr_priv_ring_pending_f() | 45 | eng_intr_mask; |
43 | | mc_intr_ltc_pending_f() | ||
44 | | mc_intr_pbus_pending_f() | ||
45 | | eng_intr_mask; | ||
46 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | 46 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), |
47 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | 47 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); |
48 | } | 48 | } |