diff options
author | Aparna Das <aparnad@nvidia.com> | 2017-10-30 18:55:11 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-01 21:10:41 -0400 |
commit | a37cec19f0cf5212cbd472cd8d94acaa1e1cff6d (patch) | |
tree | 4caa513f13333d7d2c47fd9059f2c682c46915a4 /drivers/gpu/nvgpu | |
parent | 6fdf03e0b2617ea99803bfea3e730aa69cf40188 (diff) |
gpu: nvgpu: vgpu: modify tsg enable sequence
TSG enable sequence in native has been modified due to a
hardware bug requiring enabling all channels with NEXT and
CTX_RELOAD set in a TSG, and then enabling rest of channels.
However it is not possible to check if NEXT and CTX_RELOAD
is set in vgpu. Have a separate implementation for enabling
tsg sequence in vgpu till the fix for hardware bug is
implemented for virtualized configuration.
Bug 200348087
Change-Id: I6bfc52138bc540c0ea0ad18a85155eeff6f9efa8
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588740
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/tsg_vgpu.c | 13 |
4 files changed, 16 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h index c5a51f97..aa95cc41 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | |||
@@ -61,5 +61,6 @@ int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
61 | struct channel_gk20a *ch); | 61 | struct channel_gk20a *ch); |
62 | int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); | 62 | int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); |
63 | int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); | 63 | int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); |
64 | int vgpu_enable_tsg(struct tsg_gk20a *tsg); | ||
64 | 65 | ||
65 | #endif | 66 | #endif |
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c index bc6d2e69..05295fa0 100644 --- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c | |||
@@ -275,7 +275,7 @@ static const struct gpu_ops vgpu_gm20b_ops = { | |||
275 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | 275 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, |
276 | .preempt_channel = vgpu_fifo_preempt_channel, | 276 | .preempt_channel = vgpu_fifo_preempt_channel, |
277 | .preempt_tsg = vgpu_fifo_preempt_tsg, | 277 | .preempt_tsg = vgpu_fifo_preempt_tsg, |
278 | .enable_tsg = gk20a_enable_tsg, | 278 | .enable_tsg = vgpu_enable_tsg, |
279 | .disable_tsg = gk20a_disable_tsg, | 279 | .disable_tsg = gk20a_disable_tsg, |
280 | .tsg_verify_channel_status = NULL, | 280 | .tsg_verify_channel_status = NULL, |
281 | .tsg_verify_status_ctx_reload = NULL, | 281 | .tsg_verify_status_ctx_reload = NULL, |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index b8d09b88..04fb286a 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -300,7 +300,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
300 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | 300 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, |
301 | .preempt_channel = vgpu_fifo_preempt_channel, | 301 | .preempt_channel = vgpu_fifo_preempt_channel, |
302 | .preempt_tsg = vgpu_fifo_preempt_tsg, | 302 | .preempt_tsg = vgpu_fifo_preempt_tsg, |
303 | .enable_tsg = gk20a_enable_tsg, | 303 | .enable_tsg = vgpu_enable_tsg, |
304 | .disable_tsg = gk20a_disable_tsg, | 304 | .disable_tsg = gk20a_disable_tsg, |
305 | .tsg_verify_channel_status = NULL, | 305 | .tsg_verify_channel_status = NULL, |
306 | .tsg_verify_status_ctx_reload = NULL, | 306 | .tsg_verify_status_ctx_reload = NULL, |
diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c index 2be102e3..94d7140e 100644 --- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c | |||
@@ -53,6 +53,19 @@ int vgpu_tsg_open(struct tsg_gk20a *tsg) | |||
53 | return err; | 53 | return err; |
54 | } | 54 | } |
55 | 55 | ||
56 | int vgpu_enable_tsg(struct tsg_gk20a *tsg) | ||
57 | { | ||
58 | struct gk20a *g = tsg->g; | ||
59 | struct channel_gk20a *ch; | ||
60 | |||
61 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); | ||
62 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) | ||
63 | g->ops.fifo.enable_channel(ch); | ||
64 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | ||
65 | |||
66 | return 0; | ||
67 | } | ||
68 | |||
56 | int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, | 69 | int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, |
57 | struct channel_gk20a *ch) | 70 | struct channel_gk20a *ch) |
58 | { | 71 | { |