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authorPeter Daifuku <pdaifuku@nvidia.com>2020-01-14 14:14:38 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2020-01-22 12:10:37 -0500
commit9e9046f03cf3125067666dc652499a4b7f39d9c0 (patch)
treec1a76bb88d494d50e00b6836a8502d8ebfe46668 /drivers/gpu/nvgpu
parenteb429023cf513c06f027fee8bf0b07f0bb3e6ddd (diff)
gpu: nvgpu: add struct nvgpu_sched_ctrl to gk20a
Add struct nvgpu_sched_ctrl to struct gk20a Delete struct gk20a_sched_ctrl from struct nvgpu_os_linux Update sched_ctrl functions to use the nvgpu_sched_ctrl struct Bug 200576520 Change-Id: I35b13219e5ef0a8a03333dfd7d46e1d308aec541 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279152 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/gk20a.h4
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/sched.h42
-rw-r--r--drivers/gpu/nvgpu/os/linux/debug_sched.c5
-rw-r--r--drivers/gpu/nvgpu/os/linux/ioctl_tsg.c11
-rw-r--r--drivers/gpu/nvgpu/os/linux/os_linux.h4
-rw-r--r--drivers/gpu/nvgpu/os/linux/sched.c103
-rw-r--r--drivers/gpu/nvgpu/os/linux/sched.h21
7 files changed, 99 insertions, 91 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 238329be..a0af0c5c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * GK20A Graphics 4 * GK20A Graphics
5 * 5 *
@@ -71,6 +71,7 @@ struct nvgpu_setup_bind_args;
71#include <nvgpu/ecc.h> 71#include <nvgpu/ecc.h>
72#include <nvgpu/tsg.h> 72#include <nvgpu/tsg.h>
73#include <nvgpu/sec2.h> 73#include <nvgpu/sec2.h>
74#include <nvgpu/sched.h>
74 75
75#include "gk20a/clk_gk20a.h" 76#include "gk20a/clk_gk20a.h"
76#include "gk20a/ce2_gk20a.h" 77#include "gk20a/ce2_gk20a.h"
@@ -1478,6 +1479,7 @@ struct gk20a {
1478 struct pmgr_pmupstate pmgr_pmu; 1479 struct pmgr_pmupstate pmgr_pmu;
1479 struct therm_pmupstate therm_pmu; 1480 struct therm_pmupstate therm_pmu;
1480 struct nvgpu_sec2 sec2; 1481 struct nvgpu_sec2 sec2;
1482 struct nvgpu_sched_ctrl sched_ctrl;
1481 1483
1482#ifdef CONFIG_DEBUG_FS 1484#ifdef CONFIG_DEBUG_FS
1483 struct railgate_stats pstats; 1485 struct railgate_stats pstats;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/sched.h b/drivers/gpu/nvgpu/include/nvgpu/sched.h
new file mode 100644
index 00000000..c49b7d1a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/sched.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef __NVGPU_SCHED_COMMON_H
23#define __NVGPU_SCHED_COMMON_H
24
25struct nvgpu_sched_ctrl {
26 struct nvgpu_mutex control_lock;
27 bool control_locked;
28 bool sw_ready;
29 struct nvgpu_mutex status_lock;
30 struct nvgpu_mutex busy_lock;
31
32 u64 status;
33
34 size_t bitmap_size;
35 u64 *active_tsg_bitmap;
36 u64 *recent_tsg_bitmap;
37 u64 *ref_tsg_bitmap;
38
39 struct nvgpu_cond readout_wq;
40};
41
42#endif /* __NVGPU_SCHED_COMMON_H */
diff --git a/drivers/gpu/nvgpu/os/linux/debug_sched.c b/drivers/gpu/nvgpu/os/linux/debug_sched.c
index 5b7cbddf..fa43dc49 100644
--- a/drivers/gpu/nvgpu/os/linux/debug_sched.c
+++ b/drivers/gpu/nvgpu/os/linux/debug_sched.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2017 NVIDIA Corporation. All rights reserved. 2 * Copyright (C) 2017-2020 NVIDIA Corporation. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -21,8 +21,7 @@
21static int gk20a_sched_debugfs_show(struct seq_file *s, void *unused) 21static int gk20a_sched_debugfs_show(struct seq_file *s, void *unused)
22{ 22{
23 struct gk20a *g = s->private; 23 struct gk20a *g = s->private;
24 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 24 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
25 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
26 bool sched_busy = true; 25 bool sched_busy = true;
27 26
28 int n = sched->bitmap_size / sizeof(u64); 27 int n = sched->bitmap_size / sizeof(u64);
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c
index c5079bd6..a26559f5 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -58,8 +58,7 @@ static int gk20a_tsg_bind_channel_fd(struct tsg_gk20a *tsg, int ch_fd)
58static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g, 58static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
59 struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg) 59 struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg)
60{ 60{
61 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 61 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
62 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
63 struct channel_gk20a *ch; 62 struct channel_gk20a *ch;
64 struct gr_gk20a *gr = &g->gr; 63 struct gr_gk20a *gr = &g->gr;
65 int err = 0; 64 int err = 0;
@@ -484,8 +483,7 @@ int nvgpu_ioctl_tsg_dev_release(struct inode *inode, struct file *filp)
484static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g, 483static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g,
485 struct tsg_gk20a *tsg, struct nvgpu_runlist_interleave_args *arg) 484 struct tsg_gk20a *tsg, struct nvgpu_runlist_interleave_args *arg)
486{ 485{
487 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 486 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
488 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
489 u32 level = arg->level; 487 u32 level = arg->level;
490 int err; 488 int err;
491 489
@@ -514,8 +512,7 @@ done:
514static int gk20a_tsg_ioctl_set_timeslice(struct gk20a *g, 512static int gk20a_tsg_ioctl_set_timeslice(struct gk20a *g,
515 struct tsg_gk20a *tsg, struct nvgpu_timeslice_args *arg) 513 struct tsg_gk20a *tsg, struct nvgpu_timeslice_args *arg)
516{ 514{
517 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 515 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
518 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
519 int err; 516 int err;
520 517
521 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); 518 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
diff --git a/drivers/gpu/nvgpu/os/linux/os_linux.h b/drivers/gpu/nvgpu/os/linux/os_linux.h
index 5880384a..25c6c03a 100644
--- a/drivers/gpu/nvgpu/os/linux/os_linux.h
+++ b/drivers/gpu/nvgpu/os/linux/os_linux.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -167,8 +167,6 @@ struct nvgpu_os_linux {
167 167
168 struct rw_semaphore busy_lock; 168 struct rw_semaphore busy_lock;
169 169
170 struct gk20a_sched_ctrl sched_ctrl;
171
172 bool init_done; 170 bool init_done;
173}; 171};
174 172
diff --git a/drivers/gpu/nvgpu/os/linux/sched.c b/drivers/gpu/nvgpu/os/linux/sched.c
index 3cf61644..2719429c 100644
--- a/drivers/gpu/nvgpu/os/linux/sched.c
+++ b/drivers/gpu/nvgpu/os/linux/sched.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -36,8 +36,8 @@
36ssize_t gk20a_sched_dev_read(struct file *filp, char __user *buf, 36ssize_t gk20a_sched_dev_read(struct file *filp, char __user *buf,
37 size_t size, loff_t *off) 37 size_t size, loff_t *off)
38{ 38{
39 struct gk20a_sched_ctrl *sched = filp->private_data; 39 struct gk20a *g = filp->private_data;
40 struct gk20a *g = sched->g; 40 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
41 struct nvgpu_sched_event_arg event = { 0 }; 41 struct nvgpu_sched_event_arg event = { 0 };
42 int err; 42 int err;
43 43
@@ -77,8 +77,8 @@ ssize_t gk20a_sched_dev_read(struct file *filp, char __user *buf,
77 77
78unsigned int gk20a_sched_dev_poll(struct file *filp, poll_table *wait) 78unsigned int gk20a_sched_dev_poll(struct file *filp, poll_table *wait)
79{ 79{
80 struct gk20a_sched_ctrl *sched = filp->private_data; 80 struct gk20a *g = filp->private_data;
81 struct gk20a *g = sched->g; 81 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
82 unsigned int mask = 0; 82 unsigned int mask = 0;
83 83
84 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " "); 84 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " ");
@@ -92,10 +92,10 @@ unsigned int gk20a_sched_dev_poll(struct file *filp, poll_table *wait)
92 return mask; 92 return mask;
93} 93}
94 94
95static int gk20a_sched_dev_ioctl_get_tsgs(struct gk20a_sched_ctrl *sched, 95static int gk20a_sched_dev_ioctl_get_tsgs(struct gk20a *g,
96 struct nvgpu_sched_get_tsgs_args *arg) 96 struct nvgpu_sched_get_tsgs_args *arg)
97{ 97{
98 struct gk20a *g = sched->g; 98 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
99 99
100 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "size=%u buffer=%llx", 100 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "size=%u buffer=%llx",
101 arg->size, arg->buffer); 101 arg->size, arg->buffer);
@@ -116,10 +116,10 @@ static int gk20a_sched_dev_ioctl_get_tsgs(struct gk20a_sched_ctrl *sched,
116 return 0; 116 return 0;
117} 117}
118 118
119static int gk20a_sched_dev_ioctl_get_recent_tsgs(struct gk20a_sched_ctrl *sched, 119static int gk20a_sched_dev_ioctl_get_recent_tsgs(struct gk20a *g,
120 struct nvgpu_sched_get_tsgs_args *arg) 120 struct nvgpu_sched_get_tsgs_args *arg)
121{ 121{
122 struct gk20a *g = sched->g; 122 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
123 123
124 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "size=%u buffer=%llx", 124 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "size=%u buffer=%llx",
125 arg->size, arg->buffer); 125 arg->size, arg->buffer);
@@ -142,10 +142,10 @@ static int gk20a_sched_dev_ioctl_get_recent_tsgs(struct gk20a_sched_ctrl *sched,
142 return 0; 142 return 0;
143} 143}
144 144
145static int gk20a_sched_dev_ioctl_get_tsgs_by_pid(struct gk20a_sched_ctrl *sched, 145static int gk20a_sched_dev_ioctl_get_tsgs_by_pid(struct gk20a *g,
146 struct nvgpu_sched_get_tsgs_by_pid_args *arg) 146 struct nvgpu_sched_get_tsgs_by_pid_args *arg)
147{ 147{
148 struct gk20a *g = sched->g; 148 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
149 struct fifo_gk20a *f = &g->fifo; 149 struct fifo_gk20a *f = &g->fifo;
150 struct tsg_gk20a *tsg; 150 struct tsg_gk20a *tsg;
151 u64 *bitmap; 151 u64 *bitmap;
@@ -162,7 +162,7 @@ static int gk20a_sched_dev_ioctl_get_tsgs_by_pid(struct gk20a_sched_ctrl *sched,
162 return -ENOSPC; 162 return -ENOSPC;
163 } 163 }
164 164
165 bitmap = nvgpu_kzalloc(sched->g, sched->bitmap_size); 165 bitmap = nvgpu_kzalloc(g, sched->bitmap_size);
166 if (!bitmap) 166 if (!bitmap)
167 return -ENOMEM; 167 return -ENOMEM;
168 168
@@ -180,15 +180,14 @@ static int gk20a_sched_dev_ioctl_get_tsgs_by_pid(struct gk20a_sched_ctrl *sched,
180 bitmap, sched->bitmap_size)) 180 bitmap, sched->bitmap_size))
181 err = -EFAULT; 181 err = -EFAULT;
182 182
183 nvgpu_kfree(sched->g, bitmap); 183 nvgpu_kfree(g, bitmap);
184 184
185 return err; 185 return err;
186} 186}
187 187
188static int gk20a_sched_dev_ioctl_get_params(struct gk20a_sched_ctrl *sched, 188static int gk20a_sched_dev_ioctl_get_params(struct gk20a *g,
189 struct nvgpu_sched_tsg_get_params_args *arg) 189 struct nvgpu_sched_tsg_get_params_args *arg)
190{ 190{
191 struct gk20a *g = sched->g;
192 struct fifo_gk20a *f = &g->fifo; 191 struct fifo_gk20a *f = &g->fifo;
193 struct tsg_gk20a *tsg; 192 struct tsg_gk20a *tsg;
194 u32 tsgid = arg->tsgid; 193 u32 tsgid = arg->tsgid;
@@ -219,10 +218,9 @@ static int gk20a_sched_dev_ioctl_get_params(struct gk20a_sched_ctrl *sched,
219} 218}
220 219
221static int gk20a_sched_dev_ioctl_tsg_set_timeslice( 220static int gk20a_sched_dev_ioctl_tsg_set_timeslice(
222 struct gk20a_sched_ctrl *sched, 221 struct gk20a *g,
223 struct nvgpu_sched_tsg_timeslice_args *arg) 222 struct nvgpu_sched_tsg_timeslice_args *arg)
224{ 223{
225 struct gk20a *g = sched->g;
226 struct fifo_gk20a *f = &g->fifo; 224 struct fifo_gk20a *f = &g->fifo;
227 struct tsg_gk20a *tsg; 225 struct tsg_gk20a *tsg;
228 u32 tsgid = arg->tsgid; 226 u32 tsgid = arg->tsgid;
@@ -254,10 +252,9 @@ done:
254} 252}
255 253
256static int gk20a_sched_dev_ioctl_tsg_set_runlist_interleave( 254static int gk20a_sched_dev_ioctl_tsg_set_runlist_interleave(
257 struct gk20a_sched_ctrl *sched, 255 struct gk20a *g,
258 struct nvgpu_sched_tsg_runlist_interleave_args *arg) 256 struct nvgpu_sched_tsg_runlist_interleave_args *arg)
259{ 257{
260 struct gk20a *g = sched->g;
261 struct fifo_gk20a *f = &g->fifo; 258 struct fifo_gk20a *f = &g->fifo;
262 struct tsg_gk20a *tsg; 259 struct tsg_gk20a *tsg;
263 u32 tsgid = arg->tsgid; 260 u32 tsgid = arg->tsgid;
@@ -288,9 +285,9 @@ done:
288 return err; 285 return err;
289} 286}
290 287
291static int gk20a_sched_dev_ioctl_lock_control(struct gk20a_sched_ctrl *sched) 288static int gk20a_sched_dev_ioctl_lock_control(struct gk20a *g)
292{ 289{
293 struct gk20a *g = sched->g; 290 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
294 291
295 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " "); 292 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " ");
296 293
@@ -300,9 +297,9 @@ static int gk20a_sched_dev_ioctl_lock_control(struct gk20a_sched_ctrl *sched)
300 return 0; 297 return 0;
301} 298}
302 299
303static int gk20a_sched_dev_ioctl_unlock_control(struct gk20a_sched_ctrl *sched) 300static int gk20a_sched_dev_ioctl_unlock_control(struct gk20a *g)
304{ 301{
305 struct gk20a *g = sched->g; 302 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
306 303
307 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " "); 304 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " ");
308 305
@@ -312,21 +309,19 @@ static int gk20a_sched_dev_ioctl_unlock_control(struct gk20a_sched_ctrl *sched)
312 return 0; 309 return 0;
313} 310}
314 311
315static int gk20a_sched_dev_ioctl_get_api_version(struct gk20a_sched_ctrl *sched, 312static int gk20a_sched_dev_ioctl_get_api_version(struct gk20a *g,
316 struct nvgpu_sched_api_version_args *args) 313 struct nvgpu_sched_api_version_args *args)
317{ 314{
318 struct gk20a *g = sched->g;
319
320 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " "); 315 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " ");
321 316
322 args->version = NVGPU_SCHED_API_VERSION; 317 args->version = NVGPU_SCHED_API_VERSION;
323 return 0; 318 return 0;
324} 319}
325 320
326static int gk20a_sched_dev_ioctl_get_tsg(struct gk20a_sched_ctrl *sched, 321static int gk20a_sched_dev_ioctl_get_tsg(struct gk20a *g,
327 struct nvgpu_sched_tsg_refcount_args *arg) 322 struct nvgpu_sched_tsg_refcount_args *arg)
328{ 323{
329 struct gk20a *g = sched->g; 324 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
330 struct fifo_gk20a *f = &g->fifo; 325 struct fifo_gk20a *f = &g->fifo;
331 struct tsg_gk20a *tsg; 326 struct tsg_gk20a *tsg;
332 u32 tsgid = arg->tsgid; 327 u32 tsgid = arg->tsgid;
@@ -360,10 +355,10 @@ static int gk20a_sched_dev_ioctl_get_tsg(struct gk20a_sched_ctrl *sched,
360 return 0; 355 return 0;
361} 356}
362 357
363static int gk20a_sched_dev_ioctl_put_tsg(struct gk20a_sched_ctrl *sched, 358static int gk20a_sched_dev_ioctl_put_tsg(struct gk20a *g,
364 struct nvgpu_sched_tsg_refcount_args *arg) 359 struct nvgpu_sched_tsg_refcount_args *arg)
365{ 360{
366 struct gk20a *g = sched->g; 361 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
367 struct fifo_gk20a *f = &g->fifo; 362 struct fifo_gk20a *f = &g->fifo;
368 struct tsg_gk20a *tsg; 363 struct tsg_gk20a *tsg;
369 u32 tsgid = arg->tsgid; 364 u32 tsgid = arg->tsgid;
@@ -395,13 +390,13 @@ int gk20a_sched_dev_open(struct inode *inode, struct file *filp)
395 struct nvgpu_os_linux *l = container_of(inode->i_cdev, 390 struct nvgpu_os_linux *l = container_of(inode->i_cdev,
396 struct nvgpu_os_linux, sched.cdev); 391 struct nvgpu_os_linux, sched.cdev);
397 struct gk20a *g; 392 struct gk20a *g;
398 struct gk20a_sched_ctrl *sched; 393 struct nvgpu_sched_ctrl *sched;
399 int err = 0; 394 int err = 0;
400 395
401 g = gk20a_get(&l->g); 396 g = gk20a_get(&l->g);
402 if (!g) 397 if (!g)
403 return -ENODEV; 398 return -ENODEV;
404 sched = &l->sched_ctrl; 399 sched = &g->sched_ctrl;
405 400
406 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "g=%p", g); 401 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "g=%p", g);
407 402
@@ -422,7 +417,7 @@ int gk20a_sched_dev_open(struct inode *inode, struct file *filp)
422 sched->bitmap_size); 417 sched->bitmap_size);
423 memset(sched->ref_tsg_bitmap, 0, sched->bitmap_size); 418 memset(sched->ref_tsg_bitmap, 0, sched->bitmap_size);
424 419
425 filp->private_data = sched; 420 filp->private_data = g;
426 nvgpu_log(g, gpu_dbg_sched, "filp=%p sched=%p", filp, sched); 421 nvgpu_log(g, gpu_dbg_sched, "filp=%p sched=%p", filp, sched);
427 422
428free_ref: 423free_ref:
@@ -434,8 +429,7 @@ free_ref:
434long gk20a_sched_dev_ioctl(struct file *filp, unsigned int cmd, 429long gk20a_sched_dev_ioctl(struct file *filp, unsigned int cmd,
435 unsigned long arg) 430 unsigned long arg)
436{ 431{
437 struct gk20a_sched_ctrl *sched = filp->private_data; 432 struct gk20a *g = filp->private_data;
438 struct gk20a *g = sched->g;
439 u8 buf[NVGPU_CTXSW_IOCTL_MAX_ARG_SIZE]; 433 u8 buf[NVGPU_CTXSW_IOCTL_MAX_ARG_SIZE];
440 int err = 0; 434 int err = 0;
441 435
@@ -455,45 +449,45 @@ long gk20a_sched_dev_ioctl(struct file *filp, unsigned int cmd,
455 449
456 switch (cmd) { 450 switch (cmd) {
457 case NVGPU_SCHED_IOCTL_GET_TSGS: 451 case NVGPU_SCHED_IOCTL_GET_TSGS:
458 err = gk20a_sched_dev_ioctl_get_tsgs(sched, 452 err = gk20a_sched_dev_ioctl_get_tsgs(g,
459 (struct nvgpu_sched_get_tsgs_args *)buf); 453 (struct nvgpu_sched_get_tsgs_args *)buf);
460 break; 454 break;
461 case NVGPU_SCHED_IOCTL_GET_RECENT_TSGS: 455 case NVGPU_SCHED_IOCTL_GET_RECENT_TSGS:
462 err = gk20a_sched_dev_ioctl_get_recent_tsgs(sched, 456 err = gk20a_sched_dev_ioctl_get_recent_tsgs(g,
463 (struct nvgpu_sched_get_tsgs_args *)buf); 457 (struct nvgpu_sched_get_tsgs_args *)buf);
464 break; 458 break;
465 case NVGPU_SCHED_IOCTL_GET_TSGS_BY_PID: 459 case NVGPU_SCHED_IOCTL_GET_TSGS_BY_PID:
466 err = gk20a_sched_dev_ioctl_get_tsgs_by_pid(sched, 460 err = gk20a_sched_dev_ioctl_get_tsgs_by_pid(g,
467 (struct nvgpu_sched_get_tsgs_by_pid_args *)buf); 461 (struct nvgpu_sched_get_tsgs_by_pid_args *)buf);
468 break; 462 break;
469 case NVGPU_SCHED_IOCTL_TSG_GET_PARAMS: 463 case NVGPU_SCHED_IOCTL_TSG_GET_PARAMS:
470 err = gk20a_sched_dev_ioctl_get_params(sched, 464 err = gk20a_sched_dev_ioctl_get_params(g,
471 (struct nvgpu_sched_tsg_get_params_args *)buf); 465 (struct nvgpu_sched_tsg_get_params_args *)buf);
472 break; 466 break;
473 case NVGPU_SCHED_IOCTL_TSG_SET_TIMESLICE: 467 case NVGPU_SCHED_IOCTL_TSG_SET_TIMESLICE:
474 err = gk20a_sched_dev_ioctl_tsg_set_timeslice(sched, 468 err = gk20a_sched_dev_ioctl_tsg_set_timeslice(g,
475 (struct nvgpu_sched_tsg_timeslice_args *)buf); 469 (struct nvgpu_sched_tsg_timeslice_args *)buf);
476 break; 470 break;
477 case NVGPU_SCHED_IOCTL_TSG_SET_RUNLIST_INTERLEAVE: 471 case NVGPU_SCHED_IOCTL_TSG_SET_RUNLIST_INTERLEAVE:
478 err = gk20a_sched_dev_ioctl_tsg_set_runlist_interleave(sched, 472 err = gk20a_sched_dev_ioctl_tsg_set_runlist_interleave(g,
479 (struct nvgpu_sched_tsg_runlist_interleave_args *)buf); 473 (struct nvgpu_sched_tsg_runlist_interleave_args *)buf);
480 break; 474 break;
481 case NVGPU_SCHED_IOCTL_LOCK_CONTROL: 475 case NVGPU_SCHED_IOCTL_LOCK_CONTROL:
482 err = gk20a_sched_dev_ioctl_lock_control(sched); 476 err = gk20a_sched_dev_ioctl_lock_control(g);
483 break; 477 break;
484 case NVGPU_SCHED_IOCTL_UNLOCK_CONTROL: 478 case NVGPU_SCHED_IOCTL_UNLOCK_CONTROL:
485 err = gk20a_sched_dev_ioctl_unlock_control(sched); 479 err = gk20a_sched_dev_ioctl_unlock_control(g);
486 break; 480 break;
487 case NVGPU_SCHED_IOCTL_GET_API_VERSION: 481 case NVGPU_SCHED_IOCTL_GET_API_VERSION:
488 err = gk20a_sched_dev_ioctl_get_api_version(sched, 482 err = gk20a_sched_dev_ioctl_get_api_version(g,
489 (struct nvgpu_sched_api_version_args *)buf); 483 (struct nvgpu_sched_api_version_args *)buf);
490 break; 484 break;
491 case NVGPU_SCHED_IOCTL_GET_TSG: 485 case NVGPU_SCHED_IOCTL_GET_TSG:
492 err = gk20a_sched_dev_ioctl_get_tsg(sched, 486 err = gk20a_sched_dev_ioctl_get_tsg(g,
493 (struct nvgpu_sched_tsg_refcount_args *)buf); 487 (struct nvgpu_sched_tsg_refcount_args *)buf);
494 break; 488 break;
495 case NVGPU_SCHED_IOCTL_PUT_TSG: 489 case NVGPU_SCHED_IOCTL_PUT_TSG:
496 err = gk20a_sched_dev_ioctl_put_tsg(sched, 490 err = gk20a_sched_dev_ioctl_put_tsg(g,
497 (struct nvgpu_sched_tsg_refcount_args *)buf); 491 (struct nvgpu_sched_tsg_refcount_args *)buf);
498 break; 492 break;
499 default: 493 default:
@@ -516,8 +510,8 @@ long gk20a_sched_dev_ioctl(struct file *filp, unsigned int cmd,
516 510
517int gk20a_sched_dev_release(struct inode *inode, struct file *filp) 511int gk20a_sched_dev_release(struct inode *inode, struct file *filp)
518{ 512{
519 struct gk20a_sched_ctrl *sched = filp->private_data; 513 struct gk20a *g = filp->private_data;
520 struct gk20a *g = sched->g; 514 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
521 struct fifo_gk20a *f = &g->fifo; 515 struct fifo_gk20a *f = &g->fifo;
522 struct tsg_gk20a *tsg; 516 struct tsg_gk20a *tsg;
523 unsigned int tsgid; 517 unsigned int tsgid;
@@ -544,8 +538,7 @@ int gk20a_sched_dev_release(struct inode *inode, struct file *filp)
544 538
545void gk20a_sched_ctrl_tsg_added(struct gk20a *g, struct tsg_gk20a *tsg) 539void gk20a_sched_ctrl_tsg_added(struct gk20a *g, struct tsg_gk20a *tsg)
546{ 540{
547 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 541 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
548 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
549 int err; 542 int err;
550 543
551 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); 544 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
@@ -570,8 +563,7 @@ void gk20a_sched_ctrl_tsg_added(struct gk20a *g, struct tsg_gk20a *tsg)
570 563
571void gk20a_sched_ctrl_tsg_removed(struct gk20a *g, struct tsg_gk20a *tsg) 564void gk20a_sched_ctrl_tsg_removed(struct gk20a *g, struct tsg_gk20a *tsg)
572{ 565{
573 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 566 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
574 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
575 567
576 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); 568 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
577 569
@@ -593,15 +585,13 @@ void gk20a_sched_ctrl_tsg_removed(struct gk20a *g, struct tsg_gk20a *tsg)
593 585
594int gk20a_sched_ctrl_init(struct gk20a *g) 586int gk20a_sched_ctrl_init(struct gk20a *g)
595{ 587{
596 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 588 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
597 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
598 struct fifo_gk20a *f = &g->fifo; 589 struct fifo_gk20a *f = &g->fifo;
599 int err; 590 int err;
600 591
601 if (sched->sw_ready) 592 if (sched->sw_ready)
602 return 0; 593 return 0;
603 594
604 sched->g = g;
605 sched->bitmap_size = roundup(f->num_channels, 64) / 8; 595 sched->bitmap_size = roundup(f->num_channels, 64) / 8;
606 sched->status = 0; 596 sched->status = 0;
607 597
@@ -658,8 +648,7 @@ free_active:
658 648
659void gk20a_sched_ctrl_cleanup(struct gk20a *g) 649void gk20a_sched_ctrl_cleanup(struct gk20a *g)
660{ 650{
661 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 651 struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
662 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
663 652
664 nvgpu_kfree(g, sched->active_tsg_bitmap); 653 nvgpu_kfree(g, sched->active_tsg_bitmap);
665 nvgpu_kfree(g, sched->recent_tsg_bitmap); 654 nvgpu_kfree(g, sched->recent_tsg_bitmap);
diff --git a/drivers/gpu/nvgpu/os/linux/sched.h b/drivers/gpu/nvgpu/os/linux/sched.h
index a699bbea..e88f37f5 100644
--- a/drivers/gpu/nvgpu/os/linux/sched.h
+++ b/drivers/gpu/nvgpu/os/linux/sched.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -21,25 +21,6 @@ struct gpu_ops;
21struct tsg_gk20a; 21struct tsg_gk20a;
22struct poll_table_struct; 22struct poll_table_struct;
23 23
24struct gk20a_sched_ctrl {
25 struct gk20a *g;
26
27 struct nvgpu_mutex control_lock;
28 bool control_locked;
29 bool sw_ready;
30 struct nvgpu_mutex status_lock;
31 struct nvgpu_mutex busy_lock;
32
33 u64 status;
34
35 size_t bitmap_size;
36 u64 *active_tsg_bitmap;
37 u64 *recent_tsg_bitmap;
38 u64 *ref_tsg_bitmap;
39
40 struct nvgpu_cond readout_wq;
41};
42
43int gk20a_sched_dev_release(struct inode *inode, struct file *filp); 24int gk20a_sched_dev_release(struct inode *inode, struct file *filp);
44int gk20a_sched_dev_open(struct inode *inode, struct file *filp); 25int gk20a_sched_dev_open(struct inode *inode, struct file *filp);
45long gk20a_sched_dev_ioctl(struct file *, unsigned int, unsigned long); 26long gk20a_sched_dev_ioctl(struct file *, unsigned int, unsigned long);