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authorLakshmanan M <lm@nvidia.com>2016-06-02 00:09:52 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:17 -0500
commit9454529abe0ac42d15df01e36898cd2c840de9c8 (patch)
tree6d965a08f74b72aa948edcb224a4f753d86f3b90 /drivers/gpu/nvgpu
parentc8569f1ebfcdd4546d3674458684c7e1315872a4 (diff)
gpu: nvgpu: Add multiple engine and runlist support
This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r--drivers/gpu/nvgpu/Makefile2
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c7
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_ce_gp106.h (renamed from drivers/gpu/nvgpu/gp106/hw_ce2_gp106.h)18
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_proj_gp106.h4
-rw-r--r--drivers/gpu/nvgpu/gp106/hw_top_gp106.h8
-rw-r--r--drivers/gpu/nvgpu/gp10b/ce2_gp10b.c83
-rw-r--r--drivers/gpu/nvgpu/gp10b/ce_gp10b.c82
-rw-r--r--drivers/gpu/nvgpu/gp10b/ce_gp10b.h (renamed from drivers/gpu/nvgpu/gp10b/ce2_gp10b.h)15
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.c9
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c5
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c7
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ce_gp10b.h (renamed from drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h)20
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h4
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.c59
-rw-r--r--drivers/gpu/nvgpu/gp10b/therm_gp10b.c9
15 files changed, 197 insertions, 135 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 20ba4b46..89b9b13a 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -3,7 +3,7 @@ nvgpu-t18x := ../../../../nvgpu-t18x/drivers/gpu/nvgpu
3nvgpu-y += \ 3nvgpu-y += \
4 $(nvgpu-t18x)/gp10b/gr_gp10b.o \ 4 $(nvgpu-t18x)/gp10b/gr_gp10b.o \
5 $(nvgpu-t18x)/gp10b/gr_ctx_gp10b.o \ 5 $(nvgpu-t18x)/gp10b/gr_ctx_gp10b.o \
6 $(nvgpu-t18x)/gp10b/ce2_gp10b.o \ 6 $(nvgpu-t18x)/gp10b/ce_gp10b.o \
7 $(nvgpu-t18x)/gp10b/mc_gp10b.o \ 7 $(nvgpu-t18x)/gp10b/mc_gp10b.o \
8 $(nvgpu-t18x)/gp10b/fifo_gp10b.o \ 8 $(nvgpu-t18x)/gp10b/fifo_gp10b.o \
9 $(nvgpu-t18x)/gp10b/ltc_gp10b.o \ 9 $(nvgpu-t18x)/gp10b/ltc_gp10b.o \
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 5c9e012d..1dd16139 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -24,7 +24,7 @@
24#include "gp10b/mc_gp10b.h" 24#include "gp10b/mc_gp10b.h"
25#include "gp10b/ltc_gp10b.h" 25#include "gp10b/ltc_gp10b.h"
26#include "gp10b/mm_gp10b.h" 26#include "gp10b/mm_gp10b.h"
27#include "gp10b/ce2_gp10b.h" 27#include "gp10b/ce_gp10b.h"
28#include "gp10b/fb_gp10b.h" 28#include "gp10b/fb_gp10b.h"
29#include "gp10b/fifo_gp10b.h" 29#include "gp10b/fifo_gp10b.h"
30#include "gp10b/gp10b_gating_reglist.h" 30#include "gp10b/gp10b_gating_reglist.h"
@@ -149,6 +149,9 @@ static int gp106_get_litter_value(struct gk20a *g,
149 case GPU_LIT_ROP_SHARED_BASE: 149 case GPU_LIT_ROP_SHARED_BASE:
150 ret = proj_rop_shared_base_v(); 150 ret = proj_rop_shared_base_v();
151 break; 151 break;
152 case GPU_LIT_HOST_NUM_ENGINES:
153 ret = proj_host_num_engines_v();
154 break;
152 case GPU_LIT_HOST_NUM_PBDMA: 155 case GPU_LIT_HOST_NUM_PBDMA:
153 ret = proj_host_num_pbdma_v(); 156 ret = proj_host_num_pbdma_v();
154 break; 157 break;
@@ -189,7 +192,7 @@ int gp106_init_hal(struct gk20a *g)
189 gp10b_init_ltc(gops); 192 gp10b_init_ltc(gops);
190 gp10b_init_fb(gops); 193 gp10b_init_fb(gops);
191 gp10b_init_fifo(gops); 194 gp10b_init_fifo(gops);
192 gp10b_init_ce2(gops); 195 gp10b_init_ce(gops);
193 gp106_init_gr_ctx(gops); 196 gp106_init_gr_ctx(gops);
194 gp10b_init_mm(gops); 197 gp10b_init_mm(gops);
195 gp106_init_pmu_ops(gops); 198 gp106_init_pmu_ops(gops);
diff --git a/drivers/gpu/nvgpu/gp106/hw_ce2_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ce_gp106.h
index d56b930b..36311136 100644
--- a/drivers/gpu/nvgpu/gp106/hw_ce2_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/hw_ce_gp106.h
@@ -47,34 +47,34 @@
47 * comparison with unshifted values appropriate for use in field <y> 47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>. 48 * of register <x>.
49 */ 49 */
50#ifndef _hw_ce2_gp106_h_ 50#ifndef _hw_ce_gp106_h_
51#define _hw_ce2_gp106_h_ 51#define _hw_ce_gp106_h_
52 52
53static inline u32 ce2_intr_status_r(u32 i) 53static inline u32 ce_intr_status_r(u32 i)
54{ 54{
55 return 0x00104410 + i*128; 55 return 0x00104410 + i*128;
56} 56}
57static inline u32 ce2_intr_status_blockpipe_pending_f(void) 57static inline u32 ce_intr_status_blockpipe_pending_f(void)
58{ 58{
59 return 0x1; 59 return 0x1;
60} 60}
61static inline u32 ce2_intr_status_blockpipe_reset_f(void) 61static inline u32 ce_intr_status_blockpipe_reset_f(void)
62{ 62{
63 return 0x1; 63 return 0x1;
64} 64}
65static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) 65static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
66{ 66{
67 return 0x2; 67 return 0x2;
68} 68}
69static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) 69static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
70{ 70{
71 return 0x2; 71 return 0x2;
72} 72}
73static inline u32 ce2_intr_status_launcherr_pending_f(void) 73static inline u32 ce_intr_status_launcherr_pending_f(void)
74{ 74{
75 return 0x4; 75 return 0x4;
76} 76}
77static inline u32 ce2_intr_status_launcherr_reset_f(void) 77static inline u32 ce_intr_status_launcherr_reset_f(void)
78{ 78{
79 return 0x4; 79 return 0x4;
80} 80}
diff --git a/drivers/gpu/nvgpu/gp106/hw_proj_gp106.h b/drivers/gpu/nvgpu/gp106/hw_proj_gp106.h
index 0b4b86b1..01e835ec 100644
--- a/drivers/gpu/nvgpu/gp106/hw_proj_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/hw_proj_gp106.h
@@ -106,6 +106,10 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void)
106{ 106{
107 return 0x00001800; 107 return 0x00001800;
108} 108}
109static inline u32 proj_host_num_engines_v(void)
110{
111 return 0x00000009;
112}
109static inline u32 proj_host_num_pbdma_v(void) 113static inline u32 proj_host_num_pbdma_v(void)
110{ 114{
111 return 0x00000004; 115 return 0x00000004;
diff --git a/drivers/gpu/nvgpu/gp106/hw_top_gp106.h b/drivers/gpu/nvgpu/gp106/hw_top_gp106.h
index bef6b804..e833c152 100644
--- a/drivers/gpu/nvgpu/gp106/hw_top_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/hw_top_gp106.h
@@ -146,6 +146,14 @@ static inline u32 top_device_info_type_enum_copy0_f(void)
146{ 146{
147 return 0x4; 147 return 0x4;
148} 148}
149static inline u32 top_device_info_type_enum_lce_v(void)
150{
151 return 0x00000013;
152}
153static inline u32 top_device_info_type_enum_lce_f(void)
154{
155 return 0x4c;
156}
149static inline u32 top_device_info_entry_v(u32 r) 157static inline u32 top_device_info_entry_v(u32 r)
150{ 158{
151 return (r >> 0) & 0x3; 159 return (r >> 0) & 0x3;
diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c
deleted file mode 100644
index 4cb13f3b..00000000
--- a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * GK20A Graphics Copy Engine (gr host)
3 *
4 * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
21#include "hw_ce2_gp10b.h"
22#include "ce2_gp10b.h"
23
24static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
25{
26 gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
27
28 /* wake theads waiting in this channel */
29 gk20a_channel_semaphore_wakeup(g, true);
30 return ce2_intr_status_nonblockpipe_pending_f();
31}
32
33static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
34{
35 gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n");
36
37 return ce2_intr_status_blockpipe_pending_f();
38}
39
40static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr)
41{
42 gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n");
43
44 return ce2_intr_status_launcherr_pending_f();
45}
46
47static void gp10b_ce2_isr(struct gk20a *g)
48{
49 u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0));
50 u32 clear_intr = 0;
51
52 gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr);
53
54 /* clear blocking interrupts: they exibit broken behavior */
55 if (ce2_intr & ce2_intr_status_blockpipe_pending_f())
56 clear_intr |= ce2_blockpipe_isr(g, ce2_intr);
57
58 if (ce2_intr & ce2_intr_status_launcherr_pending_f())
59 clear_intr |= ce2_launcherr_isr(g, ce2_intr);
60
61 gk20a_writel(g, ce2_intr_status_r(0), clear_intr);
62 return;
63}
64
65static void gp10b_ce2_nonstall_isr(struct gk20a *g)
66{
67 u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0));
68 u32 clear_intr = 0;
69
70 gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
71
72 if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f())
73 clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr);
74
75 gk20a_writel(g, ce2_intr_status_r(0), clear_intr);
76
77 return;
78}
79void gp10b_init_ce2(struct gpu_ops *gops)
80{
81 gops->ce2.isr_stall = gp10b_ce2_isr;
82 gops->ce2.isr_nonstall = gp10b_ce2_nonstall_isr;
83}
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
new file mode 100644
index 00000000..a35c9817
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
@@ -0,0 +1,82 @@
1/*
2 * Pascal GPU series Copy Engine.
3 *
4 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.
17 */
18
19#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
20#include "hw_ce_gp10b.h"
21#include "ce_gp10b.h"
22
23static u32 ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
24{
25 gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n");
26
27 /* wake theads waiting in this channel */
28 gk20a_channel_semaphore_wakeup(g, true);
29 return ce_intr_status_nonblockpipe_pending_f();
30}
31
32static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
33{
34 gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n");
35
36 return ce_intr_status_blockpipe_pending_f();
37}
38
39static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr)
40{
41 gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n");
42
43 return ce_intr_status_launcherr_pending_f();
44}
45
46static void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
47{
48 u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
49 u32 clear_intr = 0;
50
51 gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id);
52
53 /* clear blocking interrupts: they exibit broken behavior */
54 if (ce_intr & ce_intr_status_blockpipe_pending_f())
55 clear_intr |= ce_blockpipe_isr(g, ce_intr);
56
57 if (ce_intr & ce_intr_status_launcherr_pending_f())
58 clear_intr |= ce_launcherr_isr(g, ce_intr);
59
60 gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr);
61 return;
62}
63
64static void gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
65{
66 u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
67 u32 clear_intr = 0;
68
69 gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id);
70
71 if (ce_intr & ce_intr_status_nonblockpipe_pending_f())
72 clear_intr |= ce_nonblockpipe_isr(g, ce_intr);
73
74 gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr);
75
76 return;
77}
78void gp10b_init_ce(struct gpu_ops *gops)
79{
80 gops->ce2.isr_stall = gp10b_ce_isr;
81 gops->ce2.isr_nonstall = gp10b_ce_nonstall_isr;
82}
diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
index d432d1e0..948d0454 100644
--- a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
@@ -1,9 +1,7 @@
1/* 1/*
2 * drivers/video/tegra/host/gk20a/fifo_gk20a.h 2 * Pascal GPU series Copy Engine.
3 * 3 *
4 * GK20A graphics copy engine (gr host) 4 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved.
7 * 5 *
8 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -15,15 +13,14 @@
15 * more details. 13 * more details.
16 * 14 *
17 * You should have received a copy of the GNU General Public License along with 15 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 16 * this program.
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 */ 17 */
21#ifndef __CE2_GP10B_H__ 18#ifndef __CE_GP10B_H__
22#define __CE2_GP10B_H__ 19#define __CE_GP10B_H__
23 20
24#include "gk20a/channel_gk20a.h" 21#include "gk20a/channel_gk20a.h"
25#include "gk20a/tsg_gk20a.h" 22#include "gk20a/tsg_gk20a.h"
26 23
27void gp10b_init_ce2(struct gpu_ops *gops); 24void gp10b_init_ce(struct gpu_ops *gops);
28 25
29#endif /*__CE2_GP10B_H__*/ 26#endif /*__CE2_GP10B_H__*/
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
index aa38dc54..0aa6e29e 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -188,15 +188,17 @@ static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
188 gk20a_dbg_info("engine type %d", engine_type); 188 gk20a_dbg_info("engine type %d", engine_type);
189 if (engine_type == top_device_info_type_enum_graphics_v()) 189 if (engine_type == top_device_info_type_enum_graphics_v())
190 ret = ENGINE_GR_GK20A; 190 ret = ENGINE_GR_GK20A;
191 else if (engine_type == top_device_info_type_enum_lce_v()) 191 else if (engine_type == top_device_info_type_enum_lce_v()) {
192 ret = ENGINE_CE2_GK20A; 192 /* Default assumptions - all the CE engine have separate runlist */
193 ret = ENGINE_ASYNC_CE_GK20A;
194 }
193 else 195 else
194 gk20a_err(g->dev, "unknown engine %d", engine_type); 196 gk20a_err(g->dev, "unknown engine %d", engine_type);
195 197
196 return ret; 198 return ret;
197} 199}
198 200
199void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry, 201static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
200 u32 *inst_id, u32 *pri_base, u32 *fault_id) 202 u32 *inst_id, u32 *pri_base, u32 *fault_id)
201{ 203{
202 if (top_device_info_data_type_v(table_entry) == 204 if (top_device_info_data_type_v(table_entry) ==
@@ -226,4 +228,5 @@ void gp10b_init_fifo(struct gpu_ops *gops)
226 gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; 228 gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc;
227 gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type; 229 gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type;
228 gops->fifo.device_info_data_parse = gp10b_device_info_data_parse; 230 gops->fifo.device_info_data_parse = gp10b_device_info_data_parse;
231 gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
229} 232}
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 2ba18410..607fca59 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1182,6 +1182,9 @@ static int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
1182 struct gk20a_debug_output *o) 1182 struct gk20a_debug_output *o)
1183{ 1183{
1184 struct gr_gk20a *gr = &g->gr; 1184 struct gr_gk20a *gr = &g->gr;
1185 u32 gr_engine_id;
1186
1187 gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
1185 1188
1186 gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n", 1189 gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n",
1187 gk20a_readl(g, gr_status_r())); 1190 gk20a_readl(g, gr_status_r()));
@@ -1202,7 +1205,7 @@ static int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
1202 gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR : 0x%x\n", 1205 gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR : 0x%x\n",
1203 gk20a_readl(g, gr_fecs_intr_r())); 1206 gk20a_readl(g, gr_fecs_intr_r()));
1204 gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n", 1207 gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n",
1205 gk20a_readl(g, fifo_engine_status_r(ENGINE_GR_GK20A))); 1208 gk20a_readl(g, fifo_engine_status_r(gr_engine_id)));
1206 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n", 1209 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n",
1207 gk20a_readl(g, gr_activity_0_r())); 1210 gk20a_readl(g, gr_activity_0_r()));
1208 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n", 1211 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n",
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index a75d2604..b8fffab3 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -25,7 +25,7 @@
25#include "gp10b/mc_gp10b.h" 25#include "gp10b/mc_gp10b.h"
26#include "gp10b/ltc_gp10b.h" 26#include "gp10b/ltc_gp10b.h"
27#include "gp10b/mm_gp10b.h" 27#include "gp10b/mm_gp10b.h"
28#include "gp10b/ce2_gp10b.h" 28#include "gp10b/ce_gp10b.h"
29#include "gp10b/fb_gp10b.h" 29#include "gp10b/fb_gp10b.h"
30#include "gp10b/pmu_gp10b.h" 30#include "gp10b/pmu_gp10b.h"
31#include "gp10b/gr_ctx_gp10b.h" 31#include "gp10b/gr_ctx_gp10b.h"
@@ -150,6 +150,9 @@ static int gp10b_get_litter_value(struct gk20a *g,
150 case GPU_LIT_ROP_SHARED_BASE: 150 case GPU_LIT_ROP_SHARED_BASE:
151 ret = proj_rop_shared_base_v(); 151 ret = proj_rop_shared_base_v();
152 break; 152 break;
153 case GPU_LIT_HOST_NUM_ENGINES:
154 ret = proj_host_num_engines_v();
155 break;
153 case GPU_LIT_HOST_NUM_PBDMA: 156 case GPU_LIT_HOST_NUM_PBDMA:
154 ret = proj_host_num_pbdma_v(); 157 ret = proj_host_num_pbdma_v();
155 break; 158 break;
@@ -219,7 +222,7 @@ int gp10b_init_hal(struct gk20a *g)
219 gp10b_init_ltc(gops); 222 gp10b_init_ltc(gops);
220 gp10b_init_fb(gops); 223 gp10b_init_fb(gops);
221 gp10b_init_fifo(gops); 224 gp10b_init_fifo(gops);
222 gp10b_init_ce2(gops); 225 gp10b_init_ce(gops);
223 gp10b_init_gr_ctx(gops); 226 gp10b_init_gr_ctx(gops);
224 gp10b_init_mm(gops); 227 gp10b_init_mm(gops);
225 gp10b_init_pmu_ops(gops); 228 gp10b_init_pmu_ops(gops);
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ce_gp10b.h
index b0c35a30..3f6e1470 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_ce_gp10b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -47,34 +47,34 @@
47 * comparison with unshifted values appropriate for use in field <y> 47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>. 48 * of register <x>.
49 */ 49 */
50#ifndef _hw_ce2_gp10b_h_ 50#ifndef _hw_ce_gp10b_h_
51#define _hw_ce2_gp10b_h_ 51#define _hw_ce_gp10b_h_
52 52
53static inline u32 ce2_intr_status_r(u32 i) 53static inline u32 ce_intr_status_r(u32 i)
54{ 54{
55 return 0x00104410 + i*128; 55 return 0x00104410 + i*128;
56} 56}
57static inline u32 ce2_intr_status_blockpipe_pending_f(void) 57static inline u32 ce_intr_status_blockpipe_pending_f(void)
58{ 58{
59 return 0x1; 59 return 0x1;
60} 60}
61static inline u32 ce2_intr_status_blockpipe_reset_f(void) 61static inline u32 ce_intr_status_blockpipe_reset_f(void)
62{ 62{
63 return 0x1; 63 return 0x1;
64} 64}
65static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) 65static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
66{ 66{
67 return 0x2; 67 return 0x2;
68} 68}
69static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) 69static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
70{ 70{
71 return 0x2; 71 return 0x2;
72} 72}
73static inline u32 ce2_intr_status_launcherr_pending_f(void) 73static inline u32 ce_intr_status_launcherr_pending_f(void)
74{ 74{
75 return 0x4; 75 return 0x4;
76} 76}
77static inline u32 ce2_intr_status_launcherr_reset_f(void) 77static inline u32 ce_intr_status_launcherr_reset_f(void)
78{ 78{
79 return 0x4; 79 return 0x4;
80} 80}
diff --git a/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h
index dedc5a3f..d1a60c29 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h
@@ -106,6 +106,10 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void)
106{ 106{
107 return 0x00001800; 107 return 0x00001800;
108} 108}
109static inline u32 proj_host_num_engines_v(void)
110{
111 return 0x00000002;
112}
109static inline u32 proj_host_num_pbdma_v(void) 113static inline u32 proj_host_num_pbdma_v(void)
110{ 114{
111 return 0x00000001; 115 return 0x00000001;
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 4d9573d1..eda961b6 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP20B master 2 * GP20B master
3 * 3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -101,6 +101,9 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g)
101irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) 101irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
102{ 102{
103 u32 mc_intr_0; 103 u32 mc_intr_0;
104 u32 engine_id_idx;
105 u32 active_engine_id = 0;
106 u32 engine_enum = ENGINE_INVAL_GK20A;
104 107
105 gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); 108 gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
106 109
@@ -108,11 +111,26 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
108 111
109 gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); 112 gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
110 113
111 if (mc_intr_0 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) 114 for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
112 gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); 115 active_engine_id = g->fifo.active_engines_list[engine_id_idx];
113 if (mc_intr_0 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask 116
114 && g->ops.ce2.isr_stall) 117 if (mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) {
115 g->ops.ce2.isr_stall(g); 118 engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
119 /* GR Engine */
120 if (engine_enum == ENGINE_GR_GK20A) {
121 gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
122 }
123
124 /* CE Engine */
125 if (((engine_enum == ENGINE_GRCE_GK20A) ||
126 (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
127 g->ops.ce2.isr_stall){
128 g->ops.ce2.isr_stall(g,
129 g->fifo.engine_info[active_engine_id].inst_id,
130 g->fifo.engine_info[active_engine_id].pri_base);
131 }
132 }
133 }
116 if (mc_intr_0 & mc_intr_pfifo_pending_f()) 134 if (mc_intr_0 & mc_intr_pfifo_pending_f())
117 gk20a_fifo_isr(g); 135 gk20a_fifo_isr(g);
118 if (mc_intr_0 & mc_intr_pmu_pending_f()) 136 if (mc_intr_0 & mc_intr_pmu_pending_f())
@@ -133,6 +151,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
133irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) 151irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g)
134{ 152{
135 u32 mc_intr_1; 153 u32 mc_intr_1;
154 u32 engine_id_idx;
155 u32 active_engine_id = 0;
156 u32 engine_enum = ENGINE_INVAL_GK20A;
136 157
137 gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); 158 gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
138 159
@@ -142,13 +163,27 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g)
142 163
143 if (mc_intr_1 & mc_intr_pfifo_pending_f()) 164 if (mc_intr_1 & mc_intr_pfifo_pending_f())
144 gk20a_fifo_nonstall_isr(g); 165 gk20a_fifo_nonstall_isr(g);
145 if (mc_intr_1 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask)
146 gk20a_gr_nonstall_isr(g);
147 if (mc_intr_1 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask
148 && g->ops.ce2.isr_nonstall)
149 g->ops.ce2.isr_nonstall(g);
150
151 166
167 for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
168 active_engine_id = g->fifo.active_engines_list[engine_id_idx];
169
170 if (mc_intr_1 & g->fifo.engine_info[active_engine_id].intr_mask) {
171 engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
172 /* GR Engine */
173 if (engine_enum == ENGINE_GR_GK20A) {
174 gk20a_gr_nonstall_isr(g);
175 }
176
177 /* CE Engine */
178 if (((engine_enum == ENGINE_GRCE_GK20A) ||
179 (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
180 g->ops.ce2.isr_nonstall) {
181 g->ops.ce2.isr_nonstall(g,
182 g->fifo.engine_info[active_engine_id].inst_id,
183 g->fifo.engine_info[active_engine_id].pri_base);
184 }
185 }
186 }
152 187
153 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), 188 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
154 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); 189 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
index 5763b3b1..63efc945 100644
--- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
@@ -82,13 +82,16 @@ static int gp10b_update_therm_gate_ctrl(struct gk20a *g)
82{ 82{
83 u32 gate_ctrl; 83 u32 gate_ctrl;
84 u32 engine_id; 84 u32 engine_id;
85 u32 active_engine_id = 0;
86 struct fifo_gk20a *f = &g->fifo;
85 87
86 for (engine_id = 0; engine_id < ENGINE_INVAL_GK20A; engine_id++) { 88 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
87 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine_id)); 89 active_engine_id = f->active_engines_list[engine_id];
90 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
88 gate_ctrl = set_field(gate_ctrl, 91 gate_ctrl = set_field(gate_ctrl,
89 therm_gate_ctrl_eng_delay_before_m(), 92 therm_gate_ctrl_eng_delay_before_m(),
90 therm_gate_ctrl_eng_delay_before_f(4)); 93 therm_gate_ctrl_eng_delay_before_f(4));
91 gk20a_writel(g, therm_gate_ctrl_r(engine_id), gate_ctrl); 94 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
92 } 95 }
93 96
94 return 0; 97 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 22:58:14 -0400