diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2018-05-23 14:29:08 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:06 -0400 |
commit | 943e3158bc2071757677e184e715baec620b6683 (patch) | |
tree | 69eb089773f57305037dbb0a2c8f5e4dc0202342 /drivers/gpu/nvgpu | |
parent | 69f481ded8ccb65e01effa5fe3b8ea7771e8defe (diff) |
gpu: nvgpu: add g->fifo_eng_timeout_us
Add g->fifo_eng_timeout_us to define engine timeout in microseconds.
It is initialized with GRFIFO_TIMEOUT_CHECK_PERIOD_US. In RM server
case, it can be overriden with value defined in device tree.
Jira EVLR-2674
Change-Id: I69ac2ce779fe575566c8ba48e8cd2d0e6b2d93cf
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1728391
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/driver_common.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 |
4 files changed, 9 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/driver_common.c b/drivers/gpu/nvgpu/common/linux/driver_common.c index edc8aca8..8086cb29 100644 --- a/drivers/gpu/nvgpu/common/linux/driver_common.c +++ b/drivers/gpu/nvgpu/common/linux/driver_common.c | |||
@@ -107,6 +107,7 @@ static void nvgpu_init_timeout(struct gk20a *g) | |||
107 | g->gr_idle_timeout_default = (u32)ULONG_MAX; | 107 | g->gr_idle_timeout_default = (u32)ULONG_MAX; |
108 | } | 108 | } |
109 | g->ch_wdt_timeout_ms = platform->ch_wdt_timeout_ms; | 109 | g->ch_wdt_timeout_ms = platform->ch_wdt_timeout_ms; |
110 | g->fifo_eng_timeout_us = GRFIFO_TIMEOUT_CHECK_PERIOD_US; | ||
110 | } | 111 | } |
111 | 112 | ||
112 | static void nvgpu_init_timeslice(struct gk20a *g) | 113 | static void nvgpu_init_timeslice(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 4e0e2bd1..997856aa 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -817,7 +817,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
817 | if (g->ops.fifo.apply_ctxsw_timeout_intr) | 817 | if (g->ops.fifo.apply_ctxsw_timeout_intr) |
818 | g->ops.fifo.apply_ctxsw_timeout_intr(g); | 818 | g->ops.fifo.apply_ctxsw_timeout_intr(g); |
819 | else { | 819 | else { |
820 | timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; | 820 | timeout = g->fifo_eng_timeout_us; |
821 | timeout = scale_ptimer(timeout, | 821 | timeout = scale_ptimer(timeout, |
822 | ptimer_scalingfactor10x(g->ptimer_src_freq)); | 822 | ptimer_scalingfactor10x(g->ptimer_src_freq)); |
823 | timeout |= fifo_eng_timeout_detection_enabled_f(); | 823 | timeout |= fifo_eng_timeout_detection_enabled_f(); |
@@ -2169,15 +2169,16 @@ bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch, | |||
2169 | { | 2169 | { |
2170 | bool recover = false; | 2170 | bool recover = false; |
2171 | bool progress = false; | 2171 | bool progress = false; |
2172 | struct gk20a *g = ch->g; | ||
2172 | 2173 | ||
2173 | if (gk20a_channel_get(ch)) { | 2174 | if (gk20a_channel_get(ch)) { |
2174 | recover = gk20a_channel_update_and_check_timeout(ch, | 2175 | recover = gk20a_channel_update_and_check_timeout(ch, |
2175 | GRFIFO_TIMEOUT_CHECK_PERIOD_US / 1000, | 2176 | g->fifo_eng_timeout_us / 1000, |
2176 | &progress); | 2177 | &progress); |
2177 | *verbose = ch->timeout_debug_dump; | 2178 | *verbose = ch->timeout_debug_dump; |
2178 | *ms = ch->timeout_accumulated_ms; | 2179 | *ms = ch->timeout_accumulated_ms; |
2179 | if (recover) | 2180 | if (recover) |
2180 | ch->g->ops.fifo.set_error_notifier(ch, | 2181 | g->ops.fifo.set_error_notifier(ch, |
2181 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); | 2182 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); |
2182 | 2183 | ||
2183 | gk20a_channel_put(ch); | 2184 | gk20a_channel_put(ch); |
@@ -2194,7 +2195,7 @@ bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, | |||
2194 | struct gk20a *g = tsg->g; | 2195 | struct gk20a *g = tsg->g; |
2195 | 2196 | ||
2196 | *verbose = false; | 2197 | *verbose = false; |
2197 | *ms = GRFIFO_TIMEOUT_CHECK_PERIOD_US / 1000; | 2198 | *ms = g->fifo_eng_timeout_us / 1000; |
2198 | 2199 | ||
2199 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); | 2200 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); |
2200 | 2201 | ||
@@ -2220,7 +2221,7 @@ bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, | |||
2220 | nvgpu_log_info(g, "progress on tsg=%d ch=%d", | 2221 | nvgpu_log_info(g, "progress on tsg=%d ch=%d", |
2221 | tsg->tsgid, ch->chid); | 2222 | tsg->tsgid, ch->chid); |
2222 | gk20a_channel_put(ch); | 2223 | gk20a_channel_put(ch); |
2223 | *ms = GRFIFO_TIMEOUT_CHECK_PERIOD_US / 1000; | 2224 | *ms = g->fifo_eng_timeout_us / 1000; |
2224 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, | 2225 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, |
2225 | channel_gk20a, ch_entry) { | 2226 | channel_gk20a, ch_entry) { |
2226 | if (gk20a_channel_get(ch)) { | 2227 | if (gk20a_channel_get(ch)) { |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 01e0511d..f7bec806 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1320,6 +1320,7 @@ struct gk20a { | |||
1320 | u32 gr_idle_timeout_default; | 1320 | u32 gr_idle_timeout_default; |
1321 | bool timeouts_disabled_by_user; | 1321 | bool timeouts_disabled_by_user; |
1322 | unsigned int ch_wdt_timeout_ms; | 1322 | unsigned int ch_wdt_timeout_ms; |
1323 | u32 fifo_eng_timeout_us; | ||
1323 | 1324 | ||
1324 | struct nvgpu_mutex poweron_lock; | 1325 | struct nvgpu_mutex poweron_lock; |
1325 | struct nvgpu_mutex poweroff_lock; | 1326 | struct nvgpu_mutex poweroff_lock; |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index fd014971..fdd9ecf0 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1231,7 +1231,7 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) | |||
1231 | 1231 | ||
1232 | if (nvgpu_platform_is_silicon(g)) { | 1232 | if (nvgpu_platform_is_silicon(g)) { |
1233 | /* enable ctxsw timeout */ | 1233 | /* enable ctxsw timeout */ |
1234 | timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; | 1234 | timeout = g->fifo_eng_timeout_us; |
1235 | timeout = scale_ptimer(timeout, | 1235 | timeout = scale_ptimer(timeout, |
1236 | ptimer_scalingfactor10x(g->ptimer_src_freq)); | 1236 | ptimer_scalingfactor10x(g->ptimer_src_freq)); |
1237 | timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); | 1237 | timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); |